divclk.txt

实用的任意时钟分频Verilog代码 可以任意分频的！

module divclk (clk1,clk2);
input clk1;
output clk2;
reg clk2;
reg[99:0] s1;
always @(posedge clk1 )
begin
s1<=s1+1'b1;
 if(s1==100'd19)
begin
clk2<=~clk2;
s1<=1'b0;
end
end
endmodule