divclk.fit.summary

来自「实用的任意时钟分频Verilog代码 可以任意分频的！」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Fri Aug 15 14:53:15 2008
Quartus II Version : 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
Revision Name : divclk
Top-level Entity Name : divclk
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 209 / 5,980 ( 3 % )
Total pins : 2 / 185 ( 1 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )