divclk.tan.summary

来自「实用的任意时钟分频Verilog代码 可以任意分频的！」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.064 ns
From           : clk2~reg0
To             : clk2
From Clock     : clk1
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : 128.04 MHz ( period = 7.810 ns )
From           : s1[1]
To             : s1[96]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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