ldpc.v

ldpc verilog 程序 做ldpc硬件实现的可以

		endcase
		end
	end

reg[126:0] rom_data;

always @(posedge clk)
begin
	case (velocity)
	2'b01 : 	//0.4码率
		begin					
        rom_data<=rom_data04;
		end
	2'b10 :  	//0.6码率
		begin					
		rom_data<=rom_data06;
		end
	 2'b11 :	//0.8码率
		begin					
		rom_data<=rom_data08;
		end	
	default :            // 默认0.4码率
		begin					
		rom_data<=rom_data04;
		end
	endcase	
end



reg[6:0] count;
reg[126:0] wr_data;
reg[125:0] data;
reg  wr_en;

always @(posedge clk)   // 串并转换数据位，存入fifo
	begin
	if(!reset)
		begin
		count<=7'd0;
		data<=126'd0;
		wr_data<=126'd0;
		wr_en<=1'b0;
		end
	else
		begin
		case (velocity)
		  2'b01 : 	//0.4码率
			begin					
			if(en_media34==1)
				begin
				if(count==126)
					begin
					wr_data<={data[125:0],data_media34};
					wr_en<=1'b1;
					count<=7'd0;
					end
				else
					begin
					data<= {data[124:0],data_media34};
					wr_en<=1'b0;
					count<=count+1'b1;
					end
				end
			else
				begin
				wr_en<=1'b0;
				end		
			end
		  2'b10 :  	//0.6码率
			begin					
			if(en_media22==1)
				begin
				if(count==126)
					begin
					wr_data<={data[125:0],data_media22};
					wr_en<=1'b1;
					count<=7'd0;
					end
				else
					begin
					data<= {data[124:0],data_media22};
					wr_en<=1'b0;
					count<=count+1'b1;
					end
				end
			else
				begin
				wr_en<=1'b0;
				end	
			end
		  2'b11 :	//0.8码率
			begin					
			if(en_media10==1)
				begin
				if(count==126)
					begin
					wr_data<={data[125:0],data_media10};
					wr_en<=1'b1;
					count<=7'd0;
					end
				else
					begin
					data<= {data[124:0],data_media10};
					wr_en<=1'b0;
					count<=count+1'b1;
					end
				end
			else
				begin
				wr_en<=1'b0;
				end	
			end	
		default :            // 默认0.4码率
			begin					
			if(en_media34==1)
				begin
				if(count==126)
					begin
					wr_data<={data[125:0],data_media34};
					wr_en<=1'b1;
					count<=7'd0;
					end
				else
					begin
					data<= {data[124:0],data_media34};
					wr_en<=1'b0;
					count<=count+1'b1;
					end
				end
			else
				begin
				wr_en<=1'b0;
				end		
			end		
		endcase
				
	end
end


reg[126:0] data_out;
reg  data_out_en,indication,rd_en;
wire[126:0] fifo_out;

always @(posedge clk)  //控制输出
	begin
	if(!reset)
		begin
		data_out <= 127'd0;
		data_out_en <= 1'b0;
		indication <= 1'b0;
		end
	else
		begin
		if(data_in_en)
			begin
			case (velocity)
			  2'b01 : 	//0.4码率
				begin					
				if(count_row == 0) // 最后一行运算
					begin
					case (count_127)  // 输出校验位
						7'd2 :	data_out <= data_0;		7'd12 : data_out <= data_10;	7'd22 : data_out <= data_20;	7'd32 : data_out <= data_30;
						7'd3 :	data_out <= data_1;		7'd13 : data_out <= data_11;	7'd23 : data_out <= data_21;	7'd33 : data_out <= data_31;
						7'd4 :	data_out <= data_2;		7'd14 : data_out <= data_12;	7'd24 : data_out <= data_22;	7'd34 : data_out <= data_32;
						7'd5 :	data_out <= data_3;		7'd15 : data_out <= data_13;	7'd25 : data_out <= data_23;	7'd35 : data_out <= data_33;
						7'd6 :	data_out <= data_4;		7'd16 : data_out <= data_14;	7'd26 : data_out <= data_24;	7'd36 : data_out <= data_34;
						7'd7 : data_out <= data_5;		7'd17 : data_out <= data_15;	7'd27 : data_out <= data_25;
						7'd8 : data_out <= data_6;		7'd18 : data_out <= data_16;	7'd28 : data_out <= data_26;
						7'd9 : data_out <= data_7;		7'd19 : data_out <= data_17;	7'd29 : data_out <= data_27;
						7'd10 : data_out <= data_8;	7'd20 : data_out <= data_18;	7'd30 : data_out <= data_28;
						7'd11 : data_out <= data_9;	7'd21 : data_out <= data_19;	7'd31 : data_out <= data_29;
					endcase
					
					if(count_127==2) // 输出第一个127指示信号
						begin
						indication <= 1'b1;
						end
					else
						begin
						indication <= 1'b0;
						end
						
					if((count_127>=34)&&(count_127<=58))  //发出读fifo指令
						begin
						rd_en<=1'b1;						
						end
					else
						begin
						rd_en<=1'b0;
						end	
						
					if((count_127>=36)&&(count_127<=60))  //读fifo输出，输出数据位
						begin
						data_out <= fifo_out;						
						end
						
					if((count_127>=2)&&(count_127<=60)) //使能信号
						begin
						data_out_en<=1'b1;
						end
					else
						begin
						data_out_en<=1'b0;
						end	
					end
				else
					begin
					indication<= 1'b0;
					data_out_en<=1'b0;
					rd_en<=1'b0;
					end
				end
			  2'b10 :  	//0.6码率
				begin					
				if(count_row == 0) // 最后一行运算
					begin
					case (count_127)  // 输出校验位
						7'd2 :	data_out <= data_0;		7'd12 : data_out <= data_10;	7'd22 : data_out <= data_20;	//32 : data_out <= data_30;
						7'd3 :	data_out <= data_1;		7'd13 : data_out <= data_11;	7'd23 : data_out <= data_21;	//33 : data_out <= data_31;
						7'd4 :	data_out <= data_2;		7'd14 : data_out <= data_12;	7'd24 : data_out <= data_22;	//34 : data_out <= data_32;
						7'd5 :	data_out <= data_3;		7'd15 : data_out <= data_13;	//25 : data_out <= data_23;	35 : data_out <= data_33;
						7'd6 :	data_out <= data_4;		7'd16 : data_out <= data_14;	//26 : data_out <= data_24;	36 : data_out <= data_34;
						7'd7 : data_out <= data_5;		7'd17 : data_out <= data_15;	//27 : data_out <= data_25;
						7'd8 : data_out <= data_6;		7'd18 : data_out <= data_16;	//28 : data_out <= data_26;
						7'd9 : data_out <= data_7;		7'd19 : data_out <= data_17;	//29 : data_out <= data_27;
						7'd10 : data_out <= data_8;	7'd20 : data_out <= data_18;	//30 : data_out <= data_28;
						7'd11 : data_out <= data_9;	7'd21 : data_out <= data_19;	//31 : data_out <= data_29;
					endcase
					
					if(count_127==7'd2) // 输出第一个127指示信号
						begin
						indication <= 1'b1;
						end
					else
						begin
						indication <= 1'b0;
						end
						
					if((count_127>=7'd23)&&(count_127<=7'd58))  //发出读fifo指令
						begin
						rd_en<=1'b1;						
						end
					else
						begin
						rd_en<=1'b0;
						end	
						
					if((count_127>=7'd25)&&(count_127<=7'd60))  //读fifo输出，输出数据位
						begin
						data_out <= fifo_out;						
						end
						
					if((count_127>=7'd2)&&(count_127<=7'd60)) //使能信号
						begin
						data_out_en<=1'b1;
						end
					else
						begin
						data_out_en<=1'b0;
						end	
					end
				else
					begin
					indication<= 1'b0;
					data_out_en<=1'b0;
					rd_en<=1'b0;
					end
				end
			  2'b11 :	//0.8码率
				begin					
				if(count_row == 0) // 最后一行运算
					begin
					case (count_127)  // 输出校验位
						7'd2 :	data_out <= data_0;		//12 : data_out <= data_10;	22 : data_out <= data_20;	//32 : data_out <= data_30;
						7'd3 :	data_out <= data_1;		//13 : data_out <= data_11;	23 : data_out <= data_21;	//33 : data_out <= data_31;
						7'd4 :	data_out <= data_2;		//14 : data_out <= data_12;	24 : data_out <= data_22;	//34 : data_out <= data_32;
						7'd5 :	data_out <= data_3;		//15 : data_out <= data_13;	//25 : data_out <= data_23;	35 : data_out <= data_33;
						7'd6 :	data_out <= data_4;		//16 : data_out <= data_14;	//26 : data_out <= data_24;	36 : data_out <= data_34;
						7'd7 : data_out <= data_5;		//17 : data_out <= data_15;	//27 : data_out <= data_25;
						7'd8 : data_out <= data_6;		//18 : data_out <= data_16;	//28 : data_out <= data_26;
						7'd9 : data_out <= data_7;		//19 : data_out <= data_17;	//29 : data_out <= data_27;
						7'd10 : data_out <= data_8;	//20 : data_out <= data_18;	//30 : data_out <= data_28;
						//11 : data_out <= data_9;	21 : data_out <= data_19;	//31 : data_out <= data_29;
					endcase
					
					if(count_127==7'd2) // 输出第一个127指示信号
						begin
						indication <= 1'b1;
						end
					else
						begin
						indication <= 1'b0;
						end
						
					if((count_127>=7'd9)&&(count_127<=7'd58))  //发出读fifo指令
						begin
						rd_en<=1'b1;						
						end
					else
						begin
						rd_en<=1'b0;
						end	
						
					if((count_127>=7'd11)&&(count_127<=7'd60))  //读fifo输出，输出数据位
						begin