out_mux.rpt

组成原理的大作业

-- Node name is 'y7' 
-- Equation name is 'y7', type is output 
y7       =  _LC4_C28;

-- Node name is 'y8' 
-- Equation name is 'y8', type is output 
y8       =  _LC6_D5;

-- Node name is 'y9' 
-- Equation name is 'y9', type is output 
y9       =  _LC4_D5;

-- Node name is 'y10' 
-- Equation name is 'y10', type is output 
y10      =  _LC5_D5;

-- Node name is 'y11' 
-- Equation name is 'y11', type is output 
y11      =  _LC7_D5;

-- Node name is 'y12' 
-- Equation name is 'y12', type is output 
y12      =  _LC7_C28;

-- Node name is 'y13' 
-- Equation name is 'y13', type is output 
y13      =  _LC7_E29;

-- Node name is 'y14' 
-- Equation name is 'y14', type is output 
y14      =  _LC6_C28;

-- Node name is 'y15' 
-- Equation name is 'y15', type is output 
y15      =  _LC5_C28;

-- Node name is ':94' 
-- Equation name is '_LC2_C28', type is buried 
!_LC2_C28 = _LC2_C28~NOT;
_LC2_C28~NOT = LCELL( _EQ001);
  _EQ001 =  dest_ctl3
         #  dest_ctl2
         # !dest_ctl1
         #  dest_ctl0;

-- Node name is ':236' 
-- Equation name is '_LC5_C28', type is buried 
_LC5_C28 = LCELL( _EQ002);
  _EQ002 =  ad15 &  _LC2_C28
         #  f115 & !_LC2_C28;

-- Node name is ':242' 
-- Equation name is '_LC6_C28', type is buried 
_LC6_C28 = LCELL( _EQ003);
  _EQ003 =  ad14 &  _LC2_C28
         #  f114 & !_LC2_C28;

-- Node name is ':248' 
-- Equation name is '_LC7_E29', type is buried 
_LC7_E29 = LCELL( _EQ004);
  _EQ004 =  ad13 &  _LC2_C28
         #  f113 & !_LC2_C28;

-- Node name is ':254' 
-- Equation name is '_LC7_C28', type is buried 
_LC7_C28 = LCELL( _EQ005);
  _EQ005 =  ad12 &  _LC2_C28
         #  f112 & !_LC2_C28;

-- Node name is ':260' 
-- Equation name is '_LC7_D5', type is buried 
_LC7_D5  = LCELL( _EQ006);
  _EQ006 =  ad11 &  _LC2_C28
         #  f111 & !_LC2_C28;

-- Node name is ':266' 
-- Equation name is '_LC5_D5', type is buried 
_LC5_D5  = LCELL( _EQ007);
  _EQ007 =  ad10 &  _LC2_C28
         #  f110 & !_LC2_C28;

-- Node name is ':272' 
-- Equation name is '_LC4_D5', type is buried 
_LC4_D5  = LCELL( _EQ008);
  _EQ008 =  ad9 &  _LC2_C28
         #  f19 & !_LC2_C28;

-- Node name is ':278' 
-- Equation name is '_LC6_D5', type is buried 
_LC6_D5  = LCELL( _EQ009);
  _EQ009 =  ad8 &  _LC2_C28
         #  f18 & !_LC2_C28;

-- Node name is ':284' 
-- Equation name is '_LC4_C28', type is buried 
_LC4_C28 = LCELL( _EQ010);
  _EQ010 =  ad7 &  _LC2_C28
         #  f17 & !_LC2_C28;

-- Node name is ':290' 
-- Equation name is '_LC8_C28', type is buried 
_LC8_C28 = LCELL( _EQ011);
  _EQ011 =  ad6 &  _LC2_C28
         #  f16 & !_LC2_C28;

-- Node name is ':296' 
-- Equation name is '_LC3_D5', type is buried 
_LC3_D5  = LCELL( _EQ012);
  _EQ012 =  ad5 &  _LC2_C28
         #  f15 & !_LC2_C28;

-- Node name is ':302' 
-- Equation name is '_LC1_C28', type is buried 
_LC1_C28 = LCELL( _EQ013);
  _EQ013 =  ad4 &  _LC2_C28
         #  f14 & !_LC2_C28;

-- Node name is ':308' 
-- Equation name is '_LC1_D5', type is buried 
_LC1_D5  = LCELL( _EQ014);
  _EQ014 =  ad3 &  _LC2_C28
         #  f13 & !_LC2_C28;

-- Node name is ':314' 
-- Equation name is '_LC3_C28', type is buried 
_LC3_C28 = LCELL( _EQ015);
  _EQ015 =  ad2 &  _LC2_C28
         #  f12 & !_LC2_C28;

-- Node name is ':320' 
-- Equation name is '_LC2_D5', type is buried 
_LC2_D5  = LCELL( _EQ016);
  _EQ016 =  ad1 &  _LC2_C28
         #  f11 & !_LC2_C28;

-- Node name is ':326' 
-- Equation name is '_LC8_D5', type is buried 
_LC8_D5  = LCELL( _EQ017);
  _EQ017 =  ad0 &  _LC2_C28
         #  f10 & !_LC2_C28;



Project Information                             e:\max2work\运算器\out_mux.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KE' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,900K