📄 out_mux.rpt
字号:
96 - - C -- INPUT ^ 0 0 0 1 f12
63 - - - 11 INPUT ^ 0 0 0 1 f13
138 - - - 31 INPUT ^ 0 0 0 1 f14
65 - - - 09 INPUT ^ 0 0 0 1 f15
141 - - - 33 INPUT ^ 0 0 0 1 f16
17 - - C -- INPUT ^ 0 0 0 1 f17
120 - - - 14 INPUT ^ 0 0 0 1 f18
110 - - - 02 INPUT ^ 0 0 0 1 f19
22 - - D -- INPUT ^ 0 0 0 1 f110
19 - - D -- INPUT ^ 0 0 0 1 f111
128 - - - 19 INPUT ^ 0 0 0 1 f112
26 - - E -- INPUT ^ 0 0 0 1 f113
11 - - C -- INPUT ^ 0 0 0 1 f114
142 - - - 34 INPUT ^ 0 0 0 1 f115
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\max2work\运算器\out_mux.rpt
out_mux
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
88 - - D -- OUTPUT 0 1 0 0 y0
114 - - - 06 OUTPUT 0 1 0 0 y1
13 - - C -- OUTPUT 0 1 0 0 y2
113 - - - 05 OUTPUT 0 1 0 0 y3
12 - - C -- OUTPUT 0 1 0 0 y4
91 - - D -- OUTPUT 0 1 0 0 y5
133 - - - 28 OUTPUT 0 1 0 0 y6
14 - - C -- OUTPUT 0 1 0 0 y7
89 - - D -- OUTPUT 0 1 0 0 y8
21 - - D -- OUTPUT 0 1 0 0 y9
90 - - D -- OUTPUT 0 1 0 0 y10
69 - - - 06 OUTPUT 0 1 0 0 y11
18 - - C -- OUTPUT 0 1 0 0 y12
29 - - E -- OUTPUT 0 1 0 0 y13
42 - - - 28 OUTPUT 0 1 0 0 y14
46 - - - 27 OUTPUT 0 1 0 0 y15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\max2work\运算器\out_mux.rpt
out_mux
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 28 OR2 ! 4 0 0 16 :94
- 5 - C 28 OR2 2 1 1 0 :236
- 6 - C 28 OR2 2 1 1 0 :242
- 7 - E 29 OR2 2 1 1 0 :248
- 7 - C 28 OR2 2 1 1 0 :254
- 7 - D 05 OR2 2 1 1 0 :260
- 5 - D 05 OR2 2 1 1 0 :266
- 4 - D 05 OR2 2 1 1 0 :272
- 6 - D 05 OR2 2 1 1 0 :278
- 4 - C 28 OR2 2 1 1 0 :284
- 8 - C 28 OR2 2 1 1 0 :290
- 3 - D 05 OR2 2 1 1 0 :296
- 1 - C 28 OR2 2 1 1 0 :302
- 1 - D 05 OR2 2 1 1 0 :308
- 3 - C 28 OR2 2 1 1 0 :314
- 2 - D 05 OR2 2 1 1 0 :320
- 8 - D 05 OR2 2 1 1 0 :326
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\max2work\运算器\out_mux.rpt
out_mux
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 9/144( 6%) 0/ 72( 0%) 9/ 72( 12%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
D: 8/144( 5%) 12/ 72( 16%) 0/ 72( 0%) 5/16( 31%) 5/16( 31%) 0/16( 0%)
E: 2/144( 1%) 0/ 72( 0%) 2/ 72( 2%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
28: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\max2work\运算器\out_mux.rpt
out_mux
** EQUATIONS **
ad0 : INPUT;
ad1 : INPUT;
ad2 : INPUT;
ad3 : INPUT;
ad4 : INPUT;
ad5 : INPUT;
ad6 : INPUT;
ad7 : INPUT;
ad8 : INPUT;
ad9 : INPUT;
ad10 : INPUT;
ad11 : INPUT;
ad12 : INPUT;
ad13 : INPUT;
ad14 : INPUT;
ad15 : INPUT;
dest_ctl0 : INPUT;
dest_ctl1 : INPUT;
dest_ctl2 : INPUT;
dest_ctl3 : INPUT;
f10 : INPUT;
f11 : INPUT;
f12 : INPUT;
f13 : INPUT;
f14 : INPUT;
f15 : INPUT;
f16 : INPUT;
f17 : INPUT;
f18 : INPUT;
f19 : INPUT;
f110 : INPUT;
f111 : INPUT;
f112 : INPUT;
f113 : INPUT;
f114 : INPUT;
f115 : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC8_D5;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC2_D5;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC3_C28;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC1_D5;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC1_C28;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC3_D5;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC8_C28;
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