ram_regs.vhd

组成原理的大作业

---------------------------------------------------------------------------
---------------------------------------------------------------------------
--组原 Group 6;
--16位通用寄存器组
--由16个16位的寄存器组成
--与Q寄存器一样是采用异步清零方式
----------------------------------------------------------------------------
----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.myconstantlibrary.all;
use work.mylibrary.all;

entity ram_regs is

port(
		w_ctl			:	in std_logic;						--字/字节控制信号；
      	clk,rst			: 	in std_logic;
      	a,b 			: 	in std_logic_vector(3 downto 0);	--A,B地址；
      	f1 				: 	in std_logic_vector(15 downto 0);	--存储数据;
      	dest_ctl 		: 	in std_logic_vector(3 downto 0);	--数据输出控制信号;
		ram_0,ram_7,ram_15
						:	in std_logic;
      	ram0,ram7,ram15 : 	out std_logic;					  
      	ad,bd 			: 	buffer std_logic_vector(15 downto 0)--从通用寄存器组取出的数据;
	 );

end ram_regs;

architecture archram_regs of ram_regs is

		signal ram_en : std_logic;
	  	signal data : std_logic_vector( 15 downto 0);
        signal ab_data : ram_array;

begin

process(clk,rst,a,b,f1,dest_ctl)

	begin

      	--选择是否需要对寄存器组内容进行更新操作;
		--根据数据输出控制信号进行数据选择;
        if(dest_ctl=qreg or dest_ctl=nop) then 	
			ram_en<='0';data<="0000000000000000";ram0<='0';ram7<='0';ram15<='0';
        elsif(dest_ctl=ramqu or dest_ctl=ramu) then
		 	ram_en<='1';ram0<='0';
			if w_ctl='1' then data<=f1(14 downto 0) & ram_0;ram15<=f1(15);ram7<='0';
			else data<="00000000" & f1(6 downto 0) & ram_0;ram15<='0';ram7<=f1(7);
			end if;
        elsif(dest_ctl=ramqd or dest_ctl=ramd) then 	
			ram_en<='1';ram0<=f1(0);
			if w_ctl='1' then data<=ram_15 & f1(15 downto 1);
			else data<="00000000"& ram_7 &f1(7 downto 1);
			end if;  
        elsif(dest_ctl=rama or dest_ctl=ramf or dest_ctl=ramq) then 
			ram_en<='1';ram0<='0';ram7<='0';ram15<='0';
			if w_ctl='1' then data<=f1;
			else data<="00000000" & f1(7 downto 0);
			end if;
	  	else
	  	end if;
		   		
		--对通用寄存器组进行数据存储;
	    if rst='1' then
			for i in 0 to 15 loop
	           ab_data(i)<="0000000000000000";
			end loop;
        elsif (clk'event and clk='1') then
           if ram_en='1'then 
              ab_data(conv_integer(b)) <= data;	--存储新值;
           end if;
        end if;
		
		--从寄存器组取ad,bd两个数据;
		ad<=ab_data (conv_integer(a));	
	    bd<=ab_data (conv_integer(b));	

end process;

end archram_regs;