main.vhd

组成原理的大作业

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--组原 Group 6;
--顶层模块,即主函数MAIN；
--封装所有设计模块,包括ALU,Q_REG,RAM_REGS,SRC_OP,OUT_MUX；
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.componentslib.all;

entity main is

port (
		w_ctl					:	in std_logic;	--字/字节运算控制信号
        clk, rst,load			: 	in std_logic;	--寄存器控制信号：时钟，清零，加载；
        a, b 					: 	in std_logic_vector ( 3 downto 0);	--A,B口地址;
        d 						: 	in std_logic_vector ( 15 downto 0); --立即数据
        i 						: 	in std_logic_vector ( 11 downto 0);	--11位控制信号;
        c_n 					: 	in std_logic;	--最低位进位;
        ram_0,ram_7,ram_15 		: 	in std_logic;	
        qs_0,qs_7,qs_15 		: 	in std_logic;
		ram0,ram7,ram15 		: 	out std_logic;	
        qs0,qs7,qs15 			: 	out std_logic;
        y 						: 	buffer std_logic_vector ( 15 downto 0);	--运算器输出结果;
        sign, zero, ovr, c_n_8, c_n_16,c_n_32
							    : 	buffer std_logic	--结果标志位:符号,零,溢出,最高位进位;	
      );

end main;
  
architecture archmain of main is

alias dest_ctl : std_logic_vector ( 3 downto 0) is i (11 downto 8);	--输出控制信号
alias alu_ctl  : std_logic_vector (3 downto 0) is i ( 7 downto 4);	--运算功能控制信号
alias src_ctl  : std_logic_vector (3 downto 0) is i ( 3 downto 0);	--数据源控制信号
signal ad, bd, q, r, s, f1,f2 : std_logic_vector ( 15 downto 0);
signal ssign, szero, sovr, sc_n_8, sc_n_16,sc_n_32 :	std_logic;

begin 

u1 : ram_regs port map (w_ctl,clk, rst, a, b, f1, dest_ctl, ram_0,ram_7,ram_15,ram0,ram7,ram15, ad, bd);
u2 : alu port map (w_ctl,r, s, c_n, alu_ctl, f1,f2,sc_n_32,sc_n_16,sc_n_8, sovr, szero, ssign);
u3 : out_mux port map ( ad, f1, dest_ctl,y );
u4 : q_reg port map ( w_ctl,clk, rst,load, f1,f2, dest_ctl, qs_0,qs_7,qs_15,qs0,qs7,qs15, q);
u5 : src_op port map ( d, ad, bd, q, src_ctl, r, s);

process (clk)
	begin
	if clk'event and clk = '1' then
		sign <= ssign;
		zero <= szero;
		ovr  <= sovr;
		c_n_8<= sc_n_8;
		c_n_16<= sc_n_16;
		c_n_32<= sc_n_32;
	end if;
end process;
end archmain;