📄 main.pin
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-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
----------------------------------------------------------------------------
CHIP "main" ASSIGNED TO AN EP1K100FC256-1
DATA0 : A1
~PIN001 : A2
GND : A3
~PIN030 : A4
i3 : A5
i1 : A6
~PIN049 : A7
~PIN043 : A8
c_n : A9
|alu:u2|:64526 : A10
RESERVED : A11
~PIN019 : A12
RESERVED : A13
GND : A14
ram15 : A15
ram7 : A16
nCE : B1
DCLK : B2
i5 : B3
~PIN022 : B4
|alu:u2|:64544 : B5
~PIN020 : B6
|alu:u2|:64562 : B7
~PIN027 : B8
w_ctl : B9
qs_0 : B10
~PIN015 : B11
RESERVED : B12
RESERVED : B13
|src_op:u5|:458 : B14
TCK : B15
nCEO : B16
~PIN037 : C1
TDI : C2
~PIN009 : C3
~PIN014 : C4
|alu:u2|:64538 : C5
d15 : C6
GND : C7
~PIN042 : C8
b1 : C9
qs_15 : C10
RESERVED : C11
qs0 : C12
RESERVED : C13
|src_op:u5|:482 : C14
CONF_DONE : C15
TDO : C16
i11 : D1
i8 : D2
sign : D3
|alu:u2|:64550 : D4
|alu:u2|:7842 : D5
d0 : D6
|alu:u2|:7836 : D7
~PIN046 : D8
~PIN002 : D9
ram_15 : D10
RESERVED : D11
VCCIO : D12
RESERVED : D13
ram0 : D14
~PIN039 : D15
~PIN038 : D16
d5 : E1
d1 : E2
~PIN021 : E3
i2 : E4
GND : E5
VCCIO : E6
~PIN045 : E7
b0 : E8
|alu:u2|:62650 : E9
|src_op:u5|:470 : E10
VCCINT : E11
GND : E12
y1 : E13
i9 : E14
d2 : E15
d9 : E16
~PIN026 : F1
|alu:u2|:61348 : F2
|src_op:u5|:242 : F3
d7 : F4
VCCINT : F5
GND : F6
VCCINT : F7
VCCIO : F8
VCCINT : F9
VCCIO : F10
GND : F11
VCCINT : F12
d11 : F13
d8 : F14
~PIN029 : F15
|alu:u2|:60140 : F16
y15 : G1
|src_op:u5|:518 : G2
~PIN048 : G3
~PIN047 : G4
d10 : G5
VCCIO : G6
GND : G7
VCCIO : G8
GND : G9
GND : G10
VCCIO : G11
|alu:u2|:63952 : G12
|alu:u2|:67514 : G13
y4 : G14
y3 : G15
|src_op:u5|:233 : G16
|src_op:u5|:260 : H1
c_n_16 : H2
y6 : H3
ovr : H4
qs15 : H5
VCCINT : H6
VCCINT : H7
GND : H8
GND : H9
VCCINT : H10
VCCIO : H11
y8 : H12
|alu:u2|:61999 : H13
|alu:u2|:48093 : H14
|src_op:u5|:224 : H15
|alu:u2|:50697 : H16
y2 : J1
y0 : J2
y14 : J3
qs7 : J4
RESERVED : J5
VCCIO : J6
VCCINT : J7
GND : J8
GND : J9
VCCINT : J10
VCCINT : J11
|src_op:u5|:278 : J12
y11 : J13
|src_op:u5|:287 : J14
~PIN040 : J15
|src_op:u5|:251 : J16
|src_op:u5|:152 : K1
~PIN033 : K2
y5 : K3
|alu:u2|~29773~2 : K4
GND : K5
VCCIO : K6
GND : K7
VCCIO : K8
VCCINT : K9
GND : K10
VCCIO : K11
~PIN032 : K12
y7 : K13
y9 : K14
~PIN034 : K15
~PIN041 : K16
GND : L1
|src_op:u5|:542 : L2
~PIN044 : L3
~PIN031 : L4
VCCINT : L5
GND : L6
VCCINT : L7
clk : L8
VCC_CKLK : L9
VCCIO : L10
GND : L11
VCCINT : L12
c_n_32 : L13
y10 : L14
c_n_8 : L15
y12 : L16
y13 : M1
|alu:u2|:9079 : M2
|alu:u2|:5147 : M3
|src_op:u5|:530 : M4
GND : M5
VCCIO : M6
d3 : M7
|alu:u2|:7830 : M8
a0 : M9
d6 : M10
VCCINT : M11
GND : M12
|src_op:u5|:494 : M13
~PIN004 : M14
|alu:u2|:5255 : M15
|alu:u2|:67538 : M16
~PIN011 : N1
~PIN018 : N2
~PIN016 : N3
nCONFIG : N4
b3 : N5
d12 : N6
i0 : N7
~PIN028 : N8
~PIN023 : N9
b2 : N10
~PIN024 : N11
VCCIO : N12
RESERVED : N13
|alu:u2|:5153 : N14
~PIN012 : N15
|src_op:u5|:269 : N16
MSEL0 : P1
~PIN017 : P2
i7 : P3
i6 : P4
~PIN007 : P5
d13 : P6
d14 : P7
~PIN025 : P8
|alu:u2|:64556 : P9
ram_0 : P10
a2 : P11
|alu:u2|:59484 : P12
RESERVED : P13
~PIN010 : P14
TMS : P15
~PIN013 : P16
MSEL1 : R1
VCCINT : R2
load : R3
i4 : R4
a3 : R5
d4 : R6
~PIN036 : R7
rst : R8
a1 : R9
ram_7 : R10
RESERVED : R11
i10 : R12
RESERVED : R13
RESERVED : R14
|src_op:u5|:506 : R15
TRST : R16
~PIN006 : T1
~PIN000 : T2
~PIN003 : T3
~PIN005 : T4
~PIN008 : T5
|alu:u2|:64532 : T6
~PIN035 : T7
GND_CKLK : T8
zero : T9
qs_7 : T10
|alu:u2|:78508 : T11
RESERVED : T12
RESERVED : T13
RESERVED : T14
RESERVED : T15
nSTATUS : T16
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