q_reg.rpt

组成原理的大作业

_LC8_F35 = LCELL( _EQ047);
  _EQ047 = !dest_ctl0 &  _LC7_F35 &  w_ctl;

-- Node name is '~550~1' 
-- Equation name is '~550~1', location is LC7_F35, type is buried.
-- synthesized logic cell 
_LC7_F35 = LCELL( _EQ048);
  _EQ048 = !dest_ctl1 & !dest_ctl2 &  dest_ctl3;

-- Node name is ':935' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ049);
  _EQ049 =  f115 &  _LC5_F35 &  w_ctl;

-- Node name is ':948' 
-- Equation name is '_LC6_C19', type is buried 
_LC6_C19 = LCELL( _EQ050);
  _EQ050 =  f215 & !_LC6_C33 &  _LC8_F35
         #  _LC5_C19 & !_LC6_C33;

-- Node name is ':959' 
-- Equation name is '_LC8_C19', type is buried 
_LC8_C19 = LCELL( _EQ051);
  _EQ051 = !dest_ctl0 &  f114 &  _LC1_C33;

-- Node name is ':960' 
-- Equation name is '_LC7_C19', type is buried 
_LC7_C19 = LCELL( _EQ052);
  _EQ052 =  _LC6_C19 & !_LC6_F35
         #  _LC4_C33 & !_LC6_F35 &  qs_15;

-- Node name is ':974' 
-- Equation name is '_LC3_C19', type is buried 
_LC3_C19 = LCELL( _EQ053);
  _EQ053 =  f114 &  _LC5_F35 &  w_ctl;

-- Node name is ':981' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = LCELL( _EQ054);
  _EQ054 =  f214 & !_LC6_C33 &  _LC8_F35
         #  _LC3_C19 & !_LC6_C33;

-- Node name is ':986' 
-- Equation name is '_LC8_C33', type is buried 
_LC8_C33 = LCELL( _EQ055);
  _EQ055 = !dest_ctl0 &  f113 &  _LC1_C33;

-- Node name is ':987' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ056);
  _EQ056 =  _LC4_C19 & !_LC6_F35
         #  f115 &  _LC4_C33 & !_LC6_F35;

-- Node name is ':1001' 
-- Equation name is '_LC7_C32', type is buried 
_LC7_C32 = LCELL( _EQ057);
  _EQ057 =  f113 &  _LC5_F35 &  w_ctl;

-- Node name is ':1008' 
-- Equation name is '_LC8_C32', type is buried 
_LC8_C32 = LCELL( _EQ058);
  _EQ058 =  f213 & !_LC6_C33 &  _LC8_F35
         # !_LC6_C33 &  _LC7_C32;

-- Node name is ':1013' 
-- Equation name is '_LC5_C33', type is buried 
_LC5_C33 = LCELL( _EQ059);
  _EQ059 = !dest_ctl0 &  f112 &  _LC1_C33;

-- Node name is ':1014' 
-- Equation name is '_LC1_C32', type is buried 
_LC1_C32 = LCELL( _EQ060);
  _EQ060 = !_LC6_F35 &  _LC8_C32
         #  f114 &  _LC4_C33 & !_LC6_F35;

-- Node name is ':1028' 
-- Equation name is '_LC2_C32', type is buried 
_LC2_C32 = LCELL( _EQ061);
  _EQ061 =  f112 &  _LC5_F35 &  w_ctl;

-- Node name is ':1035' 
-- Equation name is '_LC3_C32', type is buried 
_LC3_C32 = LCELL( _EQ062);
  _EQ062 =  f212 & !_LC6_C33 &  _LC8_F35
         #  _LC2_C32 & !_LC6_C33;

-- Node name is ':1040' 
-- Equation name is '_LC6_C32', type is buried 
_LC6_C32 = LCELL( _EQ063);
  _EQ063 = !dest_ctl0 &  f111 &  _LC1_C33;

-- Node name is ':1041' 
-- Equation name is '_LC5_C32', type is buried 
_LC5_C32 = LCELL( _EQ064);
  _EQ064 =  _LC3_C32 & !_LC6_F35
         #  f113 &  _LC4_C33 & !_LC6_F35;

-- Node name is ':1055' 
-- Equation name is '_LC6_F28', type is buried 
_LC6_F28 = LCELL( _EQ065);
  _EQ065 =  f111 &  _LC5_F35 &  w_ctl;

-- Node name is ':1062' 
-- Equation name is '_LC7_F28', type is buried 
_LC7_F28 = LCELL( _EQ066);
  _EQ066 =  f211 & !_LC6_C33 &  _LC8_F35
         # !_LC6_C33 &  _LC6_F28;

-- Node name is ':1067' 
-- Equation name is '_LC2_F35', type is buried 
_LC2_F35 = LCELL( _EQ067);
  _EQ067 = !dest_ctl0 &  f110 &  _LC1_C33;

-- Node name is ':1068' 
-- Equation name is '_LC8_F28', type is buried 
_LC8_F28 = LCELL( _EQ068);
  _EQ068 = !_LC6_F35 &  _LC7_F28
         #  f112 &  _LC4_C33 & !_LC6_F35;

-- Node name is ':1082' 
-- Equation name is '_LC1_F28', type is buried 
_LC1_F28 = LCELL( _EQ069);
  _EQ069 =  f110 &  _LC5_F35 &  w_ctl;

-- Node name is ':1089' 
-- Equation name is '_LC3_F28', type is buried 
_LC3_F28 = LCELL( _EQ070);
  _EQ070 =  f210 & !_LC6_C33 &  _LC8_F35
         #  _LC1_F28 & !_LC6_C33;

-- Node name is ':1094' 
-- Equation name is '_LC4_F35', type is buried 
_LC4_F35 = LCELL( _EQ071);
  _EQ071 = !dest_ctl0 &  f19 &  _LC1_C33;

-- Node name is ':1095' 
-- Equation name is '_LC4_F28', type is buried 
_LC4_F28 = LCELL( _EQ072);
  _EQ072 =  _LC3_F28 & !_LC6_F35
         #  f111 &  _LC4_C33 & !_LC6_F35;

-- Node name is ':1109' 
-- Equation name is '_LC7_F30', type is buried 
_LC7_F30 = LCELL( _EQ073);
  _EQ073 =  f19 &  _LC5_F35 &  w_ctl;

-- Node name is ':1116' 
-- Equation name is '_LC8_F30', type is buried 
_LC8_F30 = LCELL( _EQ074);
  _EQ074 =  f29 & !_LC6_C33 &  _LC8_F35
         # !_LC6_C33 &  _LC7_F30;

-- Node name is ':1121' 
-- Equation name is '_LC8_F24', type is buried 
_LC8_F24 = LCELL( _EQ075);
  _EQ075 = !dest_ctl0 &  f18 &  _LC1_C33;

-- Node name is ':1122' 
-- Equation name is '_LC1_F30', type is buried 
_LC1_F30 = LCELL( _EQ076);
  _EQ076 = !_LC6_F35 &  _LC8_F30
         #  f110 &  _LC4_C33 & !_LC6_F35;

-- Node name is ':1136' 
-- Equation name is '_LC2_F30', type is buried 
_LC2_F30 = LCELL( _EQ077);
  _EQ077 =  f18 &  _LC5_F35 &  w_ctl;

-- Node name is ':1143' 
-- Equation name is '_LC3_F30', type is buried 
_LC3_F30 = LCELL( _EQ078);
  _EQ078 =  f28 & !_LC6_C33 &  _LC8_F35
         #  _LC2_F30 & !_LC6_C33;

-- Node name is ':1148' 
-- Equation name is '_LC5_F30', type is buried 
_LC5_F30 = LCELL( _EQ079);
  _EQ079 = !dest_ctl0 &  f17 &  _LC1_C33;

-- Node name is ':1149' 
-- Equation name is '_LC4_F30', type is buried 
_LC4_F30 = LCELL( _EQ080);
  _EQ080 =  _LC3_F30 & !_LC6_F35
         #  f19 &  _LC4_C33 & !_LC6_F35;

-- Node name is '~1156~1' 
-- Equation name is '~1156~1', location is LC3_F35, type is buried.
-- synthesized logic cell 
_LC3_F35 = LCELL( _EQ081);
  _EQ081 = !dest_ctl0 &  _LC7_F35;

-- Node name is ':1382' 
-- Equation name is '_LC1_C33', type is buried 
_LC1_C33 = LCELL( _EQ082);
  _EQ082 =  dest_ctl1 &  dest_ctl2 & !dest_ctl3 &  w_ctl;

-- Node name is '~1400~1' 
-- Equation name is '~1400~1', location is LC2_E32, type is buried.
-- synthesized logic cell 
_LC2_E32 = LCELL( f115);

-- Node name is ':1418' 
-- Equation name is '_LC1_F35', type is buried 
!_LC1_F35 = _LC1_F35~NOT;
_LC1_F35~NOT = LCELL( _EQ083);
  _EQ083 =  w_ctl
         # !dest_ctl1
         # !dest_ctl2
         #  dest_ctl3;

-- Node name is '~1436~1' 
-- Equation name is '~1436~1', location is LC4_E16, type is buried.
-- synthesized logic cell 
_LC4_E16 = LCELL( f17);

-- Node name is '~1450~1' 
-- Equation name is '~1450~1', location is LC1_F27, type is buried.
-- synthesized logic cell 
_LC1_F27 = LCELL( _EQ084);
  _EQ084 = !dest_ctl1 &  dest_ctl2 & !dest_ctl3;

-- Node name is '~1468~1' 
-- Equation name is '~1468~1', location is LC7_A23, type is buried.
-- synthesized logic cell 
_LC7_A23 = LCELL( f10);



Project Information                               e:\max2work\运算器\q_reg.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KE' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 27,570K