📄 q_reg.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 19 DFFE + 1 2 1 0 :47
- 2 - C 33 DFFE + 1 2 1 0 :49
- 7 - C 33 DFFE + 1 2 1 0 :51
- 4 - C 32 DFFE + 1 2 1 0 :53
- 2 - F 28 DFFE + 1 2 1 0 :55
- 5 - F 28 DFFE + 1 2 1 0 :57
- 4 - F 24 DFFE + 1 2 1 0 :59
- 6 - F 30 DFFE + 1 2 1 0 :61
- 3 - F 24 DFFE + 1 1 1 0 :63
- 4 - D 25 DFFE + 1 1 1 0 :65
- 1 - D 25 DFFE + 1 1 1 0 :67
- 2 - D 34 DFFE + 1 1 1 0 :69
- 6 - D 34 DFFE + 1 1 1 0 :71
- 3 - B 19 DFFE + 1 1 1 0 :73
- 6 - B 19 DFFE + 1 1 1 0 :75
- 3 - C 33 DFFE + 1 1 1 0 :77
- 1 - F 24 OR2 s 2 2 0 1 ~366~1
- 5 - F 24 OR2 s 1 2 0 1 ~366~2
- 6 - F 24 OR2 s 1 2 0 1 ~366~3
- 7 - F 24 OR2 s 1 2 0 1 ~366~4
- 6 - D 25 OR2 s 2 2 0 1 ~372~1
- 7 - D 25 OR2 s 1 2 0 1 ~372~2
- 8 - D 25 OR2 s 1 2 0 1 ~372~3
- 2 - D 25 OR2 s 2 2 0 1 ~378~1
- 3 - D 25 OR2 s 1 2 0 1 ~378~2
- 5 - D 25 OR2 s 1 2 0 1 ~378~3
- 5 - D 34 OR2 s 2 2 0 1 ~384~1
- 7 - D 34 OR2 s 1 2 0 1 ~384~2
- 8 - D 34 OR2 s 1 2 0 1 ~384~3
- 1 - D 34 OR2 s 2 2 0 1 ~390~1
- 3 - D 34 OR2 s 1 2 0 1 ~390~2
- 4 - D 34 OR2 s 1 2 0 1 ~390~3
- 5 - B 19 OR2 s 2 2 0 1 ~396~1
- 7 - B 19 OR2 s 1 2 0 1 ~396~2
- 8 - B 19 OR2 s 1 2 0 1 ~396~3
- 1 - B 19 OR2 s 2 2 0 1 ~402~1
- 2 - B 19 OR2 s 1 2 0 1 ~402~2
- 4 - B 19 OR2 s 1 2 0 1 ~402~3
- 2 - A 23 AND2 s 0 1 0 8 ~408~1
- 3 - A 23 OR2 s 2 2 0 1 ~408~2
- 6 - C 33 OR2 s 2 2 0 15 ~408~3
- 4 - A 23 OR2 s 1 2 0 1 ~408~4
- 6 - F 35 OR2 s 1 2 0 16 ~408~5
- 1 - A 23 OR2 s 1 2 0 1 ~408~6
- 4 - C 33 AND2 2 1 0 10 :517
- 2 - F 24 AND2 2 1 0 1 :524
- 5 - F 35 AND2 s 4 0 0 9 ~537~1
- 8 - F 35 AND2 2 1 0 8 :543
- 7 - F 35 AND2 s 3 0 0 2 ~550~1
- 5 - C 19 AND2 2 1 0 1 :935
- 6 - C 19 OR2 1 3 0 1 :948
- 8 - C 19 AND2 2 1 0 1 :959
- 7 - C 19 OR2 1 3 0 1 :960
- 3 - C 19 AND2 2 1 0 1 :974
- 4 - C 19 OR2 1 3 0 1 :981
- 8 - C 33 AND2 2 1 0 1 :986
- 2 - C 19 OR2 1 3 0 1 :987
- 7 - C 32 AND2 2 1 0 1 :1001
- 8 - C 32 OR2 1 3 0 1 :1008
- 5 - C 33 AND2 2 1 0 1 :1013
- 1 - C 32 OR2 1 3 0 1 :1014
- 2 - C 32 AND2 2 1 0 1 :1028
- 3 - C 32 OR2 1 3 0 1 :1035
- 6 - C 32 AND2 2 1 0 1 :1040
- 5 - C 32 OR2 1 3 0 1 :1041
- 6 - F 28 AND2 2 1 0 1 :1055
- 7 - F 28 OR2 1 3 0 1 :1062
- 2 - F 35 AND2 2 1 0 1 :1067
- 8 - F 28 OR2 1 3 0 1 :1068
- 1 - F 28 AND2 2 1 0 1 :1082
- 3 - F 28 OR2 1 3 0 1 :1089
- 4 - F 35 AND2 2 1 0 1 :1094
- 4 - F 28 OR2 1 3 0 1 :1095
- 7 - F 30 AND2 2 1 0 1 :1109
- 8 - F 30 OR2 1 3 0 1 :1116
- 8 - F 24 AND2 2 1 0 1 :1121
- 1 - F 30 OR2 1 3 0 1 :1122
- 2 - F 30 AND2 2 1 0 1 :1136
- 3 - F 30 OR2 1 3 0 1 :1143
- 5 - F 30 AND2 2 1 0 1 :1148
- 4 - F 30 OR2 1 3 0 1 :1149
- 3 - F 35 AND2 s 1 1 0 8 ~1156~1
- 1 - C 33 AND2 4 0 0 9 :1382
- 2 - E 32 LCELL s 1 0 1 0 ~1400~1
- 1 - F 35 OR2 ! 4 0 0 1 :1418
- 4 - E 16 LCELL s 1 0 1 0 ~1436~1
- 1 - F 27 AND2 s 3 0 0 3 ~1450~1
- 7 - A 23 LCELL s 1 0 1 0 ~1468~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/144( 2%) 0/ 72( 0%) 7/ 72( 9%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
B: 3/144( 2%) 0/ 72( 0%) 9/ 72( 12%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
C: 10/144( 6%) 0/ 72( 0%) 18/ 72( 25%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
D: 8/144( 5%) 0/ 72( 0%) 9/ 72( 12%) 6/16( 37%) 4/16( 25%) 0/16( 0%)
E: 0/144( 0%) 1/ 72( 1%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
F: 10/144( 6%) 0/ 72( 0%) 21/ 72( 29%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
35: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
36: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 rst
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** EQUATIONS **
clk : INPUT;
dest_ctl0 : INPUT;
dest_ctl1 : INPUT;
dest_ctl2 : INPUT;
dest_ctl3 : INPUT;
f10 : INPUT;
f11 : INPUT;
f12 : INPUT;
f13 : INPUT;
f14 : INPUT;
f15 : INPUT;
f16 : INPUT;
f17 : INPUT;
f18 : INPUT;
f19 : INPUT;
f20 : INPUT;
f21 : INPUT;
f22 : INPUT;
f23 : INPUT;
f24 : INPUT;
f25 : INPUT;
f26 : INPUT;
f27 : INPUT;
f28 : INPUT;
f29 : INPUT;
f110 : INPUT;
f111 : INPUT;
f112 : INPUT;
f113 : INPUT;
f114 : INPUT;
f115 : INPUT;
f210 : INPUT;
f211 : INPUT;
f212 : INPUT;
f213 : INPUT;
f214 : INPUT;
f215 : INPUT;
load : INPUT;
qs_0 : INPUT;
qs_7 : INPUT;
qs_15 : INPUT;
rst : INPUT;
w_ctl : INPUT;
-- Node name is 'qs0'
-- Equation name is 'qs0', type is output
qs0 = TRI(_LC7_A23, _LC1_F27);
-- Node name is 'qs7'
-- Equation name is 'qs7', type is output
qs7 = TRI(_LC4_E16, _LC1_F35);
-- Node name is 'qs15'
-- Equation name is 'qs15', type is output
qs15 = TRI(_LC2_E32, _LC1_C33);
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC3_C33;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC6_B19;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC3_B19;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC6_D34;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC2_D34;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC1_D25;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC4_D25;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = _LC3_F24;
-- Node name is 'q8'
-- Equation name is 'q8', type is output
q8 = _LC6_F30;
-- Node name is 'q9'
-- Equation name is 'q9', type is output
q9 = _LC4_F24;
-- Node name is 'q10'
-- Equation name is 'q10', type is output
q10 = _LC5_F28;
-- Node name is 'q11'
-- Equation name is 'q11', type is output
q11 = _LC2_F28;
-- Node name is 'q12'
-- Equation name is 'q12', type is output
q12 = _LC4_C32;
-- Node name is 'q13'
-- Equation name is 'q13', type is output
q13 = _LC7_C33;
-- Node name is 'q14'
-- Equation name is 'q14', type is output
q14 = _LC2_C33;
-- Node name is 'q15'
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -