📄 q_reg.rpt
字号:
Project Information e:\max2work\运算器\q_reg.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/09/2007 17:33:21
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Q_REG
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
q_reg EPF10K30ETC144-1 43 19 0 0 0 % 88 5 %
User Pins: 43 19 0
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
***** Logic for device 'q_reg' compiled without errors.
Device: EPF10K30ETC144-1
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
d d
e R R R R R R R e R R R R R R R R R R R R R
s E E E E E E E s E E E E E E E E E E E E E
t S S S S S S S t V S S S S S S S S S S S S S
_ E E E E V E E E _ w C E E E E E E E V E E E E E E
f c R f R R R C R R f R c _ C R R R R R R R C R R R R R R
f 1 t V 1 G V V V f C V V 1 G V G t f c I V V V V V V V C V V V V V V
1 1 l E 1 N E E E 1 I E E q 1 N E N l 1 t N E E E E E E E I E E E E E E
0 5 2 D 2 D D D D 6 O D D 9 3 D D D 0 7 l T D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
VCCINT | 6 103 | GND
f20 | 7 102 | qs_0
qs0 | 8 101 | RESERVED
q2 | 9 100 | RESERVED
q1 | 10 99 | f21
q15 | 11 98 | f22
q14 | 12 97 | qs_15
q0 | 13 96 | f212
q12 | 14 95 | f114
GND | 15 94 | VCCIO
GND | 16 93 | VCCINT
f215 | 17 92 | f26
q13 | 18 91 | f23
q5 | 19 EPF10K30ETC144-1 90 | f24
q4 | 20 89 | f14
q6 | 21 88 | f15
q3 | 22 87 | RESERVED
f25 | 23 86 | qs7
VCCIO | 24 85 | GND
VCCINT | 25 84 | GND
RESERVED | 26 83 | RESERVED
qs15 | 27 82 | f210
RESERVED | 28 81 | f27
RESERVED | 29 80 | qs_7
f28 | 30 79 | f18
q11 | 31 78 | f29
q10 | 32 77 | ^MSEL0
q8 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
f11 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
f f f G f f d f V f R q d G f V V r c l G G R R V R R R R G R R R R V R
1 1 1 N 2 2 e 2 C 1 E 7 e N 1 C C s l o N N E E C E E E E N E E E E C E
9 3 1 D 1 1 s 1 C 1 S s D 2 C C t k a D D S S C S S S S D S S S S C S
0 4 1 t 3 I 1 E t I I d E E I E E E E E E E E I E
_ O R _ N N R R O R R R R R R R R O R
c V c T T V V V V V V V V V V V
t E t E E E E E E E E E E E
l D l D D D D D D D D D D D
3 1
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A23 5/ 8( 62%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
B19 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
C19 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 14/22( 63%)
C32 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
C33 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 1/2 12/22( 54%)
D25 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
D34 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
E16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
E32 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F24 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 1/2 1/2 15/22( 68%)
F27 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F28 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 14/22( 63%)
F30 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
F35 8/ 8(100%) 4/ 8( 50%) 7/ 8( 87%) 0/2 0/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 56/96 ( 58%)
Total logic cells used: 88/1728 ( 5%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.30/4 ( 82%)
Total fan-in: 291/6912 ( 4%)
Total input pins required: 43
Total input I/O cell registers required: 0
Total output pins required: 19
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 88
Total flipflops required: 16
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 35/1728 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 5/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 24/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 8 0 0 16/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 1 8 0 8 0 0 0 0 8 0 33/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 16 0 0 0 5 8 8 0 1 8 0 8 0 9 8 8 8 0 88/0
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 0 clk
126 - - - -- INPUT ^ 0 0 0 15 dest_ctl0
49 - - - 21 INPUT ^ 0 0 0 5 dest_ctl1
142 - - - 34 INPUT ^ 0 0 0 5 dest_ctl2
43 - - - 30 INPUT ^ 0 0 0 5 dest_ctl3
144 - - - 36 INPUT ^ 0 0 0 3 f10
36 - - - 36 INPUT ^ 0 0 0 3 f11
51 - - - 20 INPUT ^ 0 0 0 3 f12
38 - - - 34 INPUT ^ 0 0 0 3 f13
89 - - D -- INPUT ^ 0 0 0 3 f14
88 - - D -- INPUT ^ 0 0 0 3 f15
135 - - - 29 INPUT ^ 0 0 0 3 f16
125 - - - -- INPUT ^ 0 0 0 4 f17
79 - - F -- INPUT ^ 0 0 0 3 f18
37 - - - 35 INPUT ^ 0 0 0 3 f19
7 - - A -- INPUT ^ 0 0 0 1 f20
99 - - B -- INPUT ^ 0 0 0 1 f21
98 - - B -- INPUT ^ 0 0 0 1 f22
91 - - D -- INPUT ^ 0 0 0 1 f23
90 - - D -- INPUT ^ 0 0 0 1 f24
23 - - D -- INPUT ^ 0 0 0 1 f25
92 - - D -- INPUT ^ 0 0 0 1 f26
81 - - F -- INPUT ^ 0 0 0 1 f27
30 - - F -- INPUT ^ 0 0 0 1 f28
78 - - F -- INPUT ^ 0 0 0 1 f29
39 - - - 33 INPUT ^ 0 0 0 3 f110
46 - - - 27 INPUT ^ 0 0 0 3 f111
140 - - - 32 INPUT ^ 0 0 0 3 f112
130 - - - 22 INPUT ^ 0 0 0 3 f113
95 - - C -- INPUT ^ 0 0 0 3 f114
143 - - - 35 INPUT ^ 0 0 0 3 f115
82 - - F -- INPUT ^ 0 0 0 1 f210
42 - - - 28 INPUT ^ 0 0 0 1 f211
96 - - C -- INPUT ^ 0 0 0 1 f212
44 - - - 29 INPUT ^ 0 0 0 1 f213
41 - - - 31 INPUT ^ 0 0 0 1 f214
17 - - C -- INPUT ^ 0 0 0 1 f215
56 - - - -- INPUT ^ 0 0 0 16 load
102 - - A -- INPUT ^ 0 0 0 1 qs_0
80 - - F -- INPUT ^ 0 0 0 1 qs_7
97 - - C -- INPUT ^ 0 0 0 1 qs_15
54 - - - -- INPUT G ^ 0 0 0 0 rst
124 - - - -- INPUT ^ 0 0 0 14 w_ctl
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\max2work\运算器\q_reg.rpt
q_reg
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - A -- TRI 0 1 0 0 qs0
86 - - E -- TRI 0 1 0 0 qs7
27 - - E -- TRI 0 1 0 0 qs15
13 - - C -- OUTPUT 0 1 0 0 q0
10 - - B -- OUTPUT 0 1 0 0 q1
9 - - B -- OUTPUT 0 1 0 0 q2
22 - - D -- OUTPUT 0 1 0 0 q3
20 - - D -- OUTPUT 0 1 0 0 q4
19 - - D -- OUTPUT 0 1 0 0 q5
21 - - D -- OUTPUT 0 1 0 0 q6
48 - - - 24 OUTPUT 0 1 0 0 q7
33 - - F -- OUTPUT 0 1 0 0 q8
131 - - - 23 OUTPUT 0 1 0 0 q9
32 - - F -- OUTPUT 0 1 0 0 q10
31 - - F -- OUTPUT 0 1 0 0 q11
14 - - C -- OUTPUT 0 1 0 0 q12
18 - - C -- OUTPUT 0 1 0 0 q13
12 - - C -- OUTPUT 0 1 0 0 q14
11 - - C -- OUTPUT 0 1 0 0 q15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -