📄 ram_regs.pin
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-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
----------------------------------------------------------------------------
CHIP "ram_regs" ASSIGNED TO AN EP1K30TC144-1
TCK : 1
CONF_DONE : 2
nCEO : 3
TDO : 4
VCCIO : 5
GND : 6
ram7 : 7
ad1 : 8
ad13 : 9
bd13 : 10
ram_0 : 11
bd0 : 12
ad0 : 13
ad6 : 14
GND : 15
VCCINT : 16
ram_15 : 17
ram0 : 18
bd5 : 19
ad15 : 20
bd15 : 21
f13 : 22
ad5 : 23
VCCIO : 24
GND : 25
ad12 : 26
bd9 : 27
ad9 : 28
bd12 : 29
ad7 : 30
bd7 : 31
ad10 : 32
bd10 : 33
TMS : 34
nSTATUS : 35
f110 : 36
f112 : 37
f18 : 38
f15 : 39
GND : 40
RESERVED : 41
f17 : 42
f113 : 43
f12 : 44
VCCIO : 45
ram15 : 46
w_ctl : 47
f10 : 48
RESERVED : 49
VCCINT : 50
RESERVED : 51
GND : 52
VCC_CKLK : 53
rst : 54
clk : 55
b0 : 56
GND_CKLK : 57
GND : 58
ad11 : 59
RESERVED : 60
VCCIO : 61
RESERVED : 62
RESERVED : 63
RESERVED : 64
RESERVED : 65
GND : 66
RESERVED : 67
RESERVED : 68
ad8 : 69
RESERVED : 70
VCCIO : 71
RESERVED : 72
RESERVED : 73
nCONFIG : 74
VCCINT : 75
MSEL1 : 76
MSEL0 : 77
dest_ctl3 : 78
dest_ctl0 : 79
dest_ctl2 : 80
dest_ctl1 : 81
RESERVED : 82
RESERVED : 83
GND : 84
VCCINT : 85
RESERVED : 86
RESERVED : 87
bd2 : 88
bd3 : 89
ad2 : 90
ad3 : 91
RESERVED : 92
GND : 93
VCCIO : 94
bd6 : 95
ad14 : 96
bd14 : 97
bd11 : 98
f111 : 99
ram_7 : 100
bd4 : 101
ad4 : 102
VCCINT : 103
GND : 104
TDI : 105
nCE : 106
DCLK : 107
DATA0 : 108
RESERVED : 109
bd8 : 110
RESERVED : 111
RESERVED : 112
RESERVED : 113
RESERVED : 114
VCCIO : 115
RESERVED : 116
RESERVED : 117
RESERVED : 118
RESERVED : 119
RESERVED : 120
RESERVED : 121
RESERVED : 122
GND : 123
a0 : 124
a1 : 125
b1 : 126
VCCINT : 127
bd1 : 128
GND : 129
f115 : 130
f16 : 131
f11 : 132
f19 : 133
VCCIO : 134
RESERVED : 135
RESERVED : 136
RESERVED : 137
a2 : 138
GND : 139
f14 : 140
a3 : 141
b3 : 142
f114 : 143
b2 : 144
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