📄 src_op.rpt
字号:
72 - - - 03 INPUT ^ 0 0 0 1 q6
119 - - - 13 INPUT ^ 0 0 0 1 q7
37 - - - 35 INPUT ^ 0 0 0 1 q8
38 - - - 34 INPUT ^ 0 0 0 1 q9
113 - - - 05 INPUT ^ 0 0 0 1 q10
136 - - - 30 INPUT ^ 0 0 0 1 q11
69 - - - 06 INPUT ^ 0 0 0 1 q12
112 - - - 04 INPUT ^ 0 0 0 1 q13
43 - - - 30 INPUT ^ 0 0 0 1 q14
95 - - C -- INPUT ^ 0 0 0 1 q15
124 - - - -- INPUT ^ 0 0 0 3 src_ctl0
125 - - - -- INPUT ^ 0 0 0 4 src_ctl1
126 - - - -- INPUT ^ 0 0 0 5 src_ctl2
55 - - - -- INPUT ^ 0 0 0 5 src_ctl3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\max2work\运算器\src_op.rpt
src_op
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
48 - - - 24 OUTPUT 0 1 0 0 r0
17 - - C -- OUTPUT 0 1 0 0 r1
99 - - B -- OUTPUT 0 1 0 0 r2
89 - - D -- OUTPUT 0 1 0 0 r3
91 - - D -- OUTPUT 0 1 0 0 r4
21 - - D -- OUTPUT 0 1 0 0 r5
27 - - E -- OUTPUT 0 1 0 0 r6
78 - - F -- OUTPUT 0 1 0 0 r7
7 - - A -- OUTPUT 0 1 0 0 r8
98 - - B -- OUTPUT 0 1 0 0 r9
116 - - - 07 OUTPUT 0 1 0 0 r10
42 - - - 28 OUTPUT 0 1 0 0 r11
8 - - A -- OUTPUT 0 1 0 0 r12
86 - - E -- OUTPUT 0 1 0 0 r13
79 - - F -- OUTPUT 0 1 0 0 r14
13 - - C -- OUTPUT 0 1 0 0 r15
131 - - - 23 OUTPUT 0 1 0 0 s0
18 - - C -- OUTPUT 0 1 0 0 s1
65 - - - 09 OUTPUT 0 1 0 0 s2
68 - - - 07 OUTPUT 0 1 0 0 s3
117 - - - 08 OUTPUT 0 1 0 0 s4
83 - - E -- OUTPUT 0 1 0 0 s5
81 - - F -- OUTPUT 0 1 0 0 s6
118 - - - 09 OUTPUT 0 1 0 0 s7
133 - - - 28 OUTPUT 0 1 0 0 s8
12 - - C -- OUTPUT 0 1 0 0 s9
82 - - F -- OUTPUT 0 1 0 0 s10
46 - - - 27 OUTPUT 0 1 0 0 s11
64 - - - 10 OUTPUT 0 1 0 0 s12
28 - - E -- OUTPUT 0 1 0 0 s13
14 - - C -- OUTPUT 0 1 0 0 s14
143 - - - 35 OUTPUT 0 1 0 0 s15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\max2work\运算器\src_op.rpt
src_op
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 02 AND2 s ! 3 0 0 16 ~151~1
- 2 - C 36 OR2 2 2 1 0 :152
- 5 - E 10 OR2 2 2 1 0 :161
- 3 - E 10 OR2 2 2 1 0 :170
- 7 - A 27 OR2 2 2 1 0 :179
- 2 - A 27 OR2 2 2 1 0 :188
- 4 - F 08 OR2 2 2 1 0 :197
- 6 - B 02 OR2 2 2 1 0 :206
- 5 - A 27 OR2 2 2 1 0 :215
- 8 - F 08 OR2 2 2 1 0 :224
- 3 - F 08 OR2 2 2 1 0 :233
- 4 - D 07 OR2 2 2 1 0 :242
- 3 - D 07 OR2 2 2 1 0 :251
- 6 - D 07 OR2 2 2 1 0 :260
- 2 - B 02 OR2 2 2 1 0 :269
- 6 - C 24 OR2 2 2 1 0 :278
- 8 - C 24 OR2 2 2 1 0 :287
- 4 - B 02 OR2 s 4 0 0 16 ~289~1
- 7 - B 02 AND2 s ! 3 0 0 17 ~331~1
- 5 - C 36 OR2 2 2 0 1 :332
- 5 - B 02 AND2 s 3 1 0 16 ~334~1
- 8 - B 02 OR2 4 0 0 16 :361
- 1 - C 36 OR2 1 2 1 0 :362
- 4 - C 36 OR2 2 2 0 1 :371
- 3 - C 36 OR2 1 2 1 0 :374
- 4 - E 10 OR2 2 2 0 1 :383
- 8 - E 10 OR2 1 2 1 0 :386
- 4 - A 27 OR2 2 2 0 1 :395
- 6 - E 10 OR2 1 2 1 0 :398
- 8 - A 27 OR2 2 2 0 1 :407
- 1 - A 27 OR2 1 2 1 0 :410
- 7 - F 08 OR2 2 2 0 1 :419
- 1 - F 08 OR2 1 2 1 0 :422
- 5 - C 24 OR2 2 2 0 1 :431
- 1 - C 24 OR2 1 2 1 0 :434
- 6 - A 27 OR2 2 2 0 1 :443
- 3 - A 27 OR2 1 2 1 0 :446
- 6 - F 08 OR2 2 2 0 1 :455
- 2 - E 10 OR2 1 2 1 0 :458
- 5 - F 08 OR2 2 2 0 1 :467
- 2 - F 08 OR2 1 2 1 0 :470
- 5 - D 07 OR2 2 2 0 1 :479
- 7 - E 10 OR2 1 2 1 0 :482
- 7 - D 07 OR2 2 2 0 1 :491
- 8 - D 07 OR2 1 2 1 0 :494
- 2 - D 07 OR2 2 2 0 1 :503
- 1 - D 07 OR2 1 2 1 0 :506
- 1 - B 02 OR2 2 2 0 1 :515
- 1 - E 10 OR2 1 2 1 0 :518
- 4 - C 24 OR2 2 2 0 1 :527
- 7 - C 24 OR2 1 2 1 0 :530
- 3 - C 24 OR2 2 2 0 1 :539
- 2 - C 24 OR2 1 2 1 0 :542
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\max2work\运算器\src_op.rpt
src_op
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/144( 6%) 0/ 72( 0%) 8/ 72( 11%) 3/16( 18%) 2/16( 12%) 0/16( 0%)
B: 2/144( 1%) 4/ 72( 5%) 0/ 72( 0%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
C: 10/144( 6%) 0/ 72( 0%) 16/ 72( 22%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
D: 13/144( 9%) 6/ 72( 8%) 0/ 72( 0%) 7/16( 43%) 3/16( 18%) 0/16( 0%)
E: 11/144( 7%) 11/ 72( 15%) 0/ 72( 0%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
F: 7/144( 4%) 13/ 72( 18%) 0/ 72( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 4/24( 16%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
28: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
29: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
30: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
31: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
34: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
35: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\max2work\运算器\src_op.rpt
src_op
** EQUATIONS **
ad0 : INPUT;
ad1 : INPUT;
ad2 : INPUT;
ad3 : INPUT;
ad4 : INPUT;
ad5 : INPUT;
ad6 : INPUT;
ad7 : INPUT;
ad8 : INPUT;
ad9 : INPUT;
ad10 : INPUT;
ad11 : INPUT;
ad12 : INPUT;
ad13 : INPUT;
ad14 : INPUT;
ad15 : INPUT;
bd0 : INPUT;
bd1 : INPUT;
bd2 : INPUT;
bd3 : INPUT;
bd4 : INPUT;
bd5 : INPUT;
bd6 : INPUT;
bd7 : INPUT;
bd8 : INPUT;
bd9 : INPUT;
bd10 : INPUT;
bd11 : INPUT;
bd12 : INPUT;
bd13 : INPUT;
bd14 : INPUT;
bd15 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
d8 : INPUT;
d9 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d14 : INPUT;
d15 : INPUT;
q0 : INPUT;
q1 : INPUT;
q2 : INPUT;
q3 : INPUT;
q4 : INPUT;
q5 : INPUT;
q6 : INPUT;
q7 : INPUT;
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