src_op.vhd

来自「组成原理的大作业」· VHDL 代码 · 共 40 行

---------------------------------------------------------------------------
---------------------------------------------------------------------------
--组原 Group 6;
--数据源选择模块,一个多路选择器,SRC_OP；
--对参加运算的数据通过数据源控制信号进行选择;
----------------------------------------------------------------------------
----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.myconstantlibrary.all;

entity src_op is

port ( 
        d, ad, bd, q 	:	in std_logic_vector ( 15 downto 0);	--数据来源;
        src_ctl 		: 	in std_logic_vector (3 downto 0);	--数据源选择控制信号;	
        r, s 			: 	buffer std_logic_vector ( 15 downto 0)	--最终参加运算的两个数据;
      );
end src_op;

architecture archsrc_op of src_op is

begin

	with src_ctl select
	r <=ad when aq | ab, 
		"0000000000000000" when zq | zb | za, 
		d when others;

	with src_ctl select
	s <=q when aq | zq | dq, 
		bd when ab |zb, 
		ad when za |da, 
		"0000000000000000" when others;

end archsrc_op;