out_mux.vhd

组成原理的大作业

----------------------------------------------------------------------------
----------------------------------------------------------------------------
--组原 Group 6;
--数据输出模块 OUT_MUX；
--通过运算器输出控制信号决定运算器输出Y的值；
----------------------------------------------------------------------------
----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.myconstantlibrary.all;

entity out_mux is

port (
       	  ad, f1 	: 	in std_logic_vector ( 15 downto 0);		--数据来源;
       	  dest_ctl 	: 	in std_logic_vector ( 3 downto 0); 		--输出控制信号;
       	  y 		: 	buffer std_logic_vector ( 15 downto 0)	--运算器输出端;
     );

end out_mux;

architecture archout_mux of out_mux is
	
begin 

output : process (ad,f1,dest_ctl)
			begin
			    if dest_ctl=rama then	--根据运算器设计，若为rama则输出为A,其他情况为F1;
					y<=ad;
				else
					y<=f1;
				end if;
		end process output;

end archout_mux;