rdff1.vhd

组成原理的大作业

library ieee;
use ieee.std_logic_1164.all;
entity rdff1 is 
port (
    clk,reset : in std_logic;
    d : in std_logic;
    q : buffer std_logic);
end rdff1;
architecture archrdff1 of rdff1 is 
begin
 p1: process (reset,clk)
  begin
   if (reset='1') then
      q <= '0';
   elsif ( clk'event and clk='1' ) then
      q <= d;
   end if;
  end process p1;
end archrdff1;