📄 ram_regs.rpt
字号:
132 - - - 26 INPUT ^ 0 0 0 3 f11
44 - - - 29 INPUT ^ 0 0 0 3 f12
22 - - D -- INPUT ^ 0 0 0 3 f13
140 - - - 32 INPUT ^ 0 0 0 3 f14
39 - - - 33 INPUT ^ 0 0 0 3 f15
131 - - - 23 INPUT ^ 0 0 0 3 f16
42 - - - 28 INPUT ^ 0 0 0 4 f17
38 - - - 34 INPUT ^ 0 0 0 1 f18
133 - - - 28 INPUT ^ 0 0 0 3 f19
36 - - - 36 INPUT ^ 0 0 0 3 f110
99 - - B -- INPUT ^ 0 0 0 3 f111
37 - - - 35 INPUT ^ 0 0 0 3 f112
43 - - - 30 INPUT ^ 0 0 0 3 f113
143 - - - 35 INPUT ^ 0 0 0 3 f114
130 - - - 22 INPUT ^ 0 0 0 3 f115
11 - - C -- INPUT ^ 0 0 0 1 ram_0
100 - - A -- INPUT ^ 0 0 0 1 ram_7
17 - - C -- INPUT ^ 0 0 0 1 ram_15
54 - - - -- INPUT G ^ 0 0 0 0 rst
47 - - - 25 INPUT ^ 0 0 0 26 w_ctl
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\max2work\运算器\ram_regs.rpt
ram_regs
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
13 - - C -- OUTPUT 0 1 0 0 ad0
8 - - A -- OUTPUT 0 1 0 0 ad1
90 - - D -- OUTPUT 0 1 0 0 ad2
91 - - D -- OUTPUT 0 1 0 0 ad3
102 - - A -- OUTPUT 0 1 0 0 ad4
23 - - D -- OUTPUT 0 1 0 0 ad5
14 - - C -- OUTPUT 0 1 0 0 ad6
30 - - F -- OUTPUT 0 1 0 0 ad7
69 - - - 06 OUTPUT 0 1 0 0 ad8
28 - - E -- OUTPUT 0 1 0 0 ad9
32 - - F -- OUTPUT 0 1 0 0 ad10
59 - - - 16 OUTPUT 0 1 0 0 ad11
26 - - E -- OUTPUT 0 1 0 0 ad12
9 - - B -- OUTPUT 0 1 0 0 ad13
96 - - C -- OUTPUT 0 1 0 0 ad14
20 - - D -- OUTPUT 0 1 0 0 ad15
12 - - C -- OUTPUT 0 1 0 0 bd0
128 - - - 19 OUTPUT 0 1 0 0 bd1
88 - - D -- OUTPUT 0 1 0 0 bd2
89 - - D -- OUTPUT 0 1 0 0 bd3
101 - - A -- OUTPUT 0 1 0 0 bd4
19 - - D -- OUTPUT 0 1 0 0 bd5
95 - - C -- OUTPUT 0 1 0 0 bd6
31 - - F -- OUTPUT 0 1 0 0 bd7
110 - - - 02 OUTPUT 0 1 0 0 bd8
27 - - E -- OUTPUT 0 1 0 0 bd9
33 - - F -- OUTPUT 0 1 0 0 bd10
98 - - B -- OUTPUT 0 1 0 0 bd11
29 - - E -- OUTPUT 0 1 0 0 bd12
10 - - B -- OUTPUT 0 1 0 0 bd13
97 - - C -- OUTPUT 0 1 0 0 bd14
21 - - D -- OUTPUT 0 1 0 0 bd15
18 - - C -- OUTPUT 0 1 0 0 ram0
7 - - A -- OUTPUT 0 1 0 0 ram7
46 - - - 27 OUTPUT 0 1 0 0 ram15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\max2work\运算器\ram_regs.rpt
ram_regs
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - D 24 DFFE + 1 2 0 2 ab_data15_15 (:87)
- 7 - C 11 DFFE + 1 2 0 2 ab_data15_14 (:88)
- 8 - B 36 DFFE + 1 2 0 2 ab_data15_13 (:89)
- 8 - E 35 DFFE + 1 2 0 2 ab_data15_12 (:90)
- 4 - B 25 DFFE + 1 2 0 2 ab_data15_11 (:91)
- 3 - F 26 DFFE + 1 2 0 2 ab_data15_10 (:92)
- 3 - E 29 DFFE + 1 2 0 2 ab_data15_9 (:93)
- 4 - A 15 DFFE + 1 2 0 2 ab_data15_8 (:94)
- 8 - F 30 DFFE + 1 2 0 2 ab_data15_7 (:95)
- 6 - C 06 DFFE + 1 2 0 2 ab_data15_6 (:96)
- 6 - D 28 DFFE + 1 2 0 2 ab_data15_5 (:97)
- 8 - A 12 DFFE + 1 2 0 2 ab_data15_4 (:98)
- 3 - D 14 DFFE + 1 2 0 2 ab_data15_3 (:99)
- 6 - D 04 DFFE + 1 2 0 2 ab_data15_2 (:100)
- 3 - A 23 DFFE + 1 2 0 2 ab_data15_1 (:101)
- 5 - C 35 DFFE + 1 2 0 2 ab_data15_0 (:102)
- 2 - D 24 DFFE + 1 2 0 2 ab_data14_15 (:103)
- 6 - C 11 DFFE + 1 2 0 2 ab_data14_14 (:104)
- 7 - B 36 DFFE + 1 2 0 2 ab_data14_13 (:105)
- 7 - E 35 DFFE + 1 2 0 2 ab_data14_12 (:106)
- 3 - B 25 DFFE + 1 2 0 2 ab_data14_11 (:107)
- 1 - F 26 DFFE + 1 2 0 2 ab_data14_10 (:108)
- 6 - E 24 DFFE + 1 2 0 2 ab_data14_9 (:109)
- 3 - A 15 DFFE + 1 2 0 2 ab_data14_8 (:110)
- 7 - F 30 DFFE + 1 2 0 2 ab_data14_7 (:111)
- 5 - C 06 DFFE + 1 2 0 2 ab_data14_6 (:112)
- 5 - D 28 DFFE + 1 2 0 2 ab_data14_5 (:113)
- 7 - A 12 DFFE + 1 2 0 2 ab_data14_4 (:114)
- 6 - D 14 DFFE + 1 2 0 2 ab_data14_3 (:115)
- 5 - D 04 DFFE + 1 2 0 2 ab_data14_2 (:116)
- 2 - A 23 DFFE + 1 2 0 2 ab_data14_1 (:117)
- 4 - C 35 DFFE + 1 2 0 2 ab_data14_0 (:118)
- 4 - D 35 DFFE + 1 2 0 2 ab_data13_15 (:119)
- 3 - C 04 DFFE + 1 2 0 2 ab_data13_14 (:120)
- 8 - B 35 DFFE + 1 2 0 2 ab_data13_13 (:121)
- 4 - E 22 DFFE + 1 2 0 2 ab_data13_12 (:122)
- 1 - B 22 DFFE + 1 2 0 2 ab_data13_11 (:123)
- 5 - F 20 DFFE + 1 2 0 2 ab_data13_10 (:124)
- 3 - E 24 DFFE + 1 2 0 2 ab_data13_9 (:125)
- 5 - A 13 DFFE + 1 2 0 2 ab_data13_8 (:126)
- 4 - F 23 DFFE + 1 2 0 2 ab_data13_7 (:127)
- 2 - C 06 DFFE + 1 2 0 2 ab_data13_6 (:128)
- 8 - D 28 DFFE + 1 2 0 2 ab_data13_5 (:129)
- 5 - A 32 DFFE + 1 2 0 2 ab_data13_4 (:130)
- 4 - D 14 DFFE + 1 2 0 2 ab_data13_3 (:131)
- 8 - D 04 DFFE + 1 2 0 2 ab_data13_2 (:132)
- 4 - A 28 DFFE + 1 2 0 2 ab_data13_1 (:133)
- 8 - C 35 DFFE + 1 2 0 2 ab_data13_0 (:134)
- 3 - D 35 DFFE + 1 2 0 2 ab_data12_15 (:135)
- 2 - C 04 DFFE + 1 2 0 2 ab_data12_14 (:136)
- 7 - B 35 DFFE + 1 2 0 2 ab_data12_13 (:137)
- 3 - E 22 DFFE + 1 2 0 2 ab_data12_12 (:138)
- 2 - B 22 DFFE + 1 2 0 2 ab_data12_11 (:139)
- 4 - F 20 DFFE + 1 2 0 2 ab_data12_10 (:140)
- 1 - E 24 DFFE + 1 2 0 2 ab_data12_9 (:141)
- 3 - A 13 DFFE + 1 2 0 2 ab_data12_8 (:142)
- 3 - F 23 DFFE + 1 2 0 2 ab_data12_7 (:143)
- 3 - C 06 DFFE + 1 2 0 2 ab_data12_6 (:144)
- 7 - D 28 DFFE + 1 2 0 2 ab_data12_5 (:145)
- 3 - A 32 DFFE + 1 2 0 2 ab_data12_4 (:146)
- 2 - D 14 DFFE + 1 2 0 2 ab_data12_3 (:147)
- 7 - D 04 DFFE + 1 2 0 2 ab_data12_2 (:148)
- 2 - A 28 DFFE + 1 2 0 2 ab_data12_1 (:149)
- 7 - C 35 DFFE + 1 2 0 2 ab_data12_0 (:150)
- 4 - D 12 DFFE + 1 2 0 2 ab_data11_15 (:151)
- 4 - C 08 DFFE + 1 2 0 2 ab_data11_14 (:152)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -