with_sdram_daq.map.rpt

fpga开发pci的verilog

Analysis & Synthesis report for WITH_SDRAM_DAQ
Tue Nov 13 15:28:43 2007
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |WITH_SDRAM_DAQ|receiver:receiver0|STATE
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Parameter Settings for User Entity Instance: dpram16k_1to512_32:dpram|altsyncram:altsyncram_component
 13. Parameter Settings for User Entity Instance: datacnt:mydatacnt
 14. Parameter Settings for User Entity Instance: fifo1k_32:fifo|dcfifo:dcfifo_component
 15. Parameter Settings for User Entity Instance: pll0:mypll|altpll:altpll_component
 16. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 17. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 18. dcfifo Parameter Settings by Entity Instance
 19. SignalTap II Logic Analyzer Settings
 20. Analysis & Synthesis Equations
 21. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Nov 13 15:28:43 2007         ;
; Quartus II Version          ; 5.0 Build 171 11/03/2005 SP 2 SJ Full Version ;
; Revision Name               ; WITH_SDRAM_DAQ                                ;
; Top-level Entity Name       ; WITH_SDRAM_DAQ                                ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 2,591                                         ;
; Total pins                  ; 123                                           ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 128,512                                       ;
; Total PLLs                  ; 1                                             ;