📄 i2c.vhd
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IF (phase2 = '1') THEN
scl_xhdl1 <= '0';
END IF;
END IF;
CASE i2c_state IS
WHEN ini =>
CASE inner_state IS
WHEN start =>
IF (phase1 = '1') THEN
link <= '1';
sda_buf <= '0';
END IF;
IF ((phase3 AND link) = '1') THEN
inner_state <= first;
sda_buf <= '1';
link <= '1';
END IF;
WHEN first =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= second;
END IF;
WHEN second =>
IF (phase3 = '1') THEN
sda_buf <= '1';
link <= '1';
inner_state <= third;
END IF;
WHEN third =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= fourth;
END IF;
WHEN fourth =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= fifth;
END IF;
WHEN fifth =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= sixth;
END IF;
WHEN sixth =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= seventh;
END IF;
WHEN seventh =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= eighth;
END IF;
WHEN eighth =>
IF (phase3 = '1') THEN
link <= '0';
inner_state <= ack;
END IF;
WHEN ack =>
IF (phase0 = '1') THEN
sda_buf <= sda;
END IF;
IF (phase1 = '1') THEN
IF (sda_buf = '1') THEN
main_state <= "00";
END IF;
END IF;
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(7);
inner_state <= first;
i2c_state <= sendaddr;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN sendaddr =>
CASE inner_state IS
WHEN first =>
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(6);
inner_state <= second;
END IF;
WHEN second =>
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(5);
inner_state <= third;
END IF;
WHEN third =>
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(4);
inner_state <= fourth;
END IF;
WHEN fourth =>
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(3);
inner_state <= fifth;
END IF;
WHEN fifth =>
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(2);
inner_state <= sixth;
END IF;
WHEN sixth =>
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(1);
inner_state <= seventh;
END IF;
WHEN seventh =>
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= addr(0);
inner_state <= eighth;
END IF;
WHEN eighth =>
IF (phase3 = '1') THEN
link <= '0';
inner_state <= ack;
END IF;
WHEN ack =>
IF (phase0 = '1') THEN
sda_buf <= sda;
END IF;
IF (phase1 = '1') THEN
IF (sda_buf = '1') THEN
main_state <= "00";
END IF;
END IF;
IF (phase3 = '1') THEN
link <= '1';
sda_buf <= '1';
inner_state <= start;
i2c_state <= read_ini;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN read_ini =>
CASE inner_state IS
WHEN start =>
IF (phase1 = '1') THEN
link <= '1';
sda_buf <= '0';
END IF;
IF ((phase3 AND link) = '1') THEN
inner_state <= first;
sda_buf <= '1';
link <= '1';
END IF;
WHEN first =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= second;
END IF;
WHEN second =>
IF (phase3 = '1') THEN
sda_buf <= '1';
link <= '1';
inner_state <= third;
END IF;
WHEN third =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= fourth;
END IF;
WHEN fourth =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= fifth;
END IF;
WHEN fifth =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= sixth;
END IF;
WHEN sixth =>
IF (phase3 = '1') THEN
sda_buf <= '0';
link <= '1';
inner_state <= seventh;
END IF;
WHEN seventh =>
IF (phase3 = '1') THEN
sda_buf <= '1';
link <= '1';
inner_state <= eighth;
END IF;
WHEN eighth =>
IF (phase3 = '1') THEN
link <= '0';
inner_state <= ack;
END IF;
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