tb_apb.v

AMBA2.0标准的AHB2APb桥

module tb_apb(
              );


reg hclk,
    hreset_n,
    hwrite_i,
    hsel_apb_i,
    hready_r_i;
reg [31:0] haddr_i,
           hwdata_i,
           prdata_i;
reg [1:0] htrans_i;


wire [31:0] hrdata_o,
            pwdata_o,
            paddr_o;
wire [6:0]	psel_slave_o;
wire [1:0] hresp_o;
wire hready_r_o;
initial
  begin
    hclk = 1'b0;
    hreset_n = 1'b0;
    hwrite_i = 1'b1;
    hsel_apb_i = 1'b1;
    haddr_i = 32'b0;
    hwdata_i = 32'b0;
    prdata_i = 32'b0;
    htrans_i = 2'b00;
    hready_r_i = 1'b1;
    #50;
    hreset_n = 1'b1;
    htrans_i = 2'b10;
    haddr_i = 32'h0001;
    hwdata_i = 32'h0000;
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
    htrans_i = 2'b11;
    haddr_i = 32'h0002;
    hwdata_i = 32'h0001;
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
    haddr_i = 32'h0003;
    hwdata_i = 32'h0002;
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
    haddr_i = 32'h0004;
    hwdata_i = 32'h0003;
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
    haddr_i = 32'h0005;
    hwdata_i = 32'h0004;
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
    haddr_i = 32'HE001C000;
    hwrite_i = 0;
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
    wait (hready_r_o == 1'b0);
    wait (hready_r_o == 1'b1);
  //  #10
    htrans_i = 0;
    #300;
    $finish;
    end


always #10 hclk = ~hclk;

top_apb top_apb(
               hclk,
               hreset_n,
               haddr_i[31:0],
               htrans_i[1:0],
               hwrite_i,
               hwdata_i[31:0],
               hsel_apb_i,
               prdata_i[31:0],
               hready_r_i,
               //hready_w_i,
               //output
               hrdata_o[31:0],
               hready_r_o,
               hresp_o[1:0],
               pwdata_o[31:0],
               penable_o,
            //   psel_uart_o,
             //  psel_i2c_o,
            //   psel_ir_o ,   //select the interrup controller
            //   psel_remap_o ,// select the remap and pause controller
            //   psel_timer_o,  // select the timer
           //    psel_pause_o,  //select pause
           		 psel_slave_o,
               paddr_o[31:0],
               pwrite_o
               );
endmodule