📄 led.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led is
port(clkin:in std_logic;
rst:in std_logic;
q:out std_logic_vector(7 downto 0)
);
end led;
architecture one of led is
type states is(s0,s1,s2,s3);
signal present:states;
signal clkout:std_logic;
signal clk1hz:std_logic;
signal q1:std_logic_vector(7 downto 0);
signal count:std_logic_vector(3 downto 0);
begin
process(clkin)
begin
clkout<=not clkin;
end process;
process(clkout)
variable m:integer range 0 to 12499999;
begin
if rising_edge(clkout) then
if m=12499999 then
clk1hz<=not clk1hz;
else
m:=m+1;
end if;
end if;
end process;
process(clk1hz,rst)
begin
if rst='0' then
present<=s0;
q1<=(others=>'0');
elsif clk1hz'event and clk1hz='1' then
case present is
when s0=>if q1="00000000" then-------------------------s0模式:从左到右逐个点亮LED
q1<="10000000";
else
if count="0111" then
count<=(others=>'0');
q1<="00000001";
present<=s1;
else
q1<=q1(0)&q1(7 downto 1);
count<=count+1;
present<=s0;
end if;
end if;
when s1=>if count="0111" then---------------------------s1模式:从右到左逐个点亮LED
count<=(others=>'0');
q1<="10000001";
present<=s2;
else
q1<=q1(6 downto 0)&q1(7);
count<=count+1;
present<=s1;
end if;
when s2=>if count="0011" then---------------------------s2模式:从两边到中间逐个点亮LED
count<=(others=>'0');
q1<="00011000";
present<=s3;
else
q1(7 downto 4)<=q1(4)&q1(7 downto 5);
q1(3 downto 0)<=q1(2 downto 0)&q1(3);
count<=count+1;
present<=s2;
end if;
when s3=>if count="0011" then---------------------------s3模式:从中间到两边逐个点亮LED
count<=(others=>'0');
q1<="10000000";
present<=s0;
else
q1(7 downto 4)<=q1(6 downto 4)&q1(7);
q1(3 downto 0)<=q1(0)&q1(3 downto 1);
count<=count+1;
present<=s3;
end if;
end case;
end if;
end process;
q<=q1;
end one;
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