mcst.txt

曼彻斯特编码实现

verilog 的曼彻斯特编码，仿真文件的代码要如何写？
module me(clk12x,data_in,start,reset,me_do_ack,data_out,me_do);
input clk12x;
input [15:0] data_in;
input start;
input reset;
input me_do_ack;
output data_out;
output me_do;

reg me_do;
reg data_out;
reg [16:0] data;
wire clk1x_t;
reg clk1x;
reg clk1x_enable;
reg [4:0] bit_sent;
reg data_word;
reg [4:0] syn1,syn0;reg [3:0] clk_div;
reg load;
//产生3位宽度的同步头

always @(posedge clk12x or posedge reset)
        begin
                if(reset)
                        begin
                                syn1<=5'b00000;
                                syn0<=5'b00000;
                                data_word<=1'b0;
                        end
                else if (start)
                        begin
                                if(clk1x_enable)
                                        data_out<=data[16]^clk1x;
                                if((!data_word)&&(!clk1x_enable))
                                        if(syn1<5'b00000)
                                                begin
                                                        syn1<=syn1+1;
                                                        data_out<=1'b1;
                                                        load<=1'b1;
                                                end
                                        else if (syn0<5'b10010)
                                                begin
                                                        syn0<=syn0+1;
                                                        data_out<=1'b0;
                                                end
                                        else if ((syn1[4] && syn1[1])&&(syn0[4] && syn0[1]))
                                                begin
                                                        data_word<=1'b1;
                                                        syn1<=5'b00000;
                                                        syn0<=5'b00000;
                                                        load<=1'b0;
                                                end
                                if((data_word) && (!clk1x_enable))
                                        if (syn0<5'b10010)
                                                begin
                                                        syn0<=syn0+1;
                                                        data_out<=1'b0;
                                                        load<=1'b1;
                                                end
                                        else if (syn1<5'b10010)
                                                begin
                                                        syn1<=syn1+1;
                                                        data_out<=1'b1;
                                                end
                                        else if ((syn1[4] && syn1[1])&&(syn0[4]&&syn0[1]))
                                                begin        
                                                        syn1<=5'b00000;
                                                        syn0<=5'b00000;
                                                        load<=1'b0;
                                                end
                                end
                        else if(!start)
                                data_word<=1'b0;
                end
//产生clk1x_enable信号
        always @(posedge clk12x or posedge reset)
                begin 
                        if(reset)
                                clk1x_enable<=1'b0;
                        else if(bit_sent[4]&& bit_sent[0])
                                clk1x_enable<=1'b0;
                        else if((syn1[4] && syn1[1]) && (syn0[4] && syn0[1]))
                        clk1x_enable<=1'b1;
                end
//load the data to be transmit and shift it
        always @(negedge clk1x or posedge reset or posedge load)
                begin 
                        if(reset)
                                data<=17'b00000000000000000;
                        else if (load)
                                begin
                                        data[16:1]<=data_in;
                                        data[0]<=!(^data_in);
                                end
                        else if (bit_sent<5'b10010)
                                begin
                                        data[16:1]<=data[15:0];
                                        data[0]<=1'b0;
                                end
                end
                
//产生编码结束信号

        always @(posedge clk12x or posedge reset)
                begin
                        if(reset)
                                me_do<=1'b1;
                        else if (bit_sent[4] && bit_sent[0])
                                me_do<=1'b1;
                        else if (me_do_ack)
                                me_do<=1'b0;
                end
                
//时钟分频

        always @(posedge clk12x or posedge reset)
                begin
                        if(reset)
                                clk_div=4'b0000;
                        else if (clk1x_enable)
                                begin
                                        if (clk_div<4'b1011)
                                                clk_div=clk_div+1;
                                        else 
                                           clk_div=4'b0000;
                                end
                end
//generate clk1x 产生 1MHz 时钟

        assign clk1x_t=!(clk_div<4'b0110);
        
        always @(posedge clk12x or posedge reset)
                begin 
                        if (reset)
                                clk1x<=1'b0;
                        else 
                                clk1x<=clk1x_t;
                end

//count the bit has been sent
        always @(negedge clk1x or posedge reset or posedge me_do_ack)
                begin 
                        if (reset)
                                bit_sent<=5'b00000;
                        else if (me_do_ack)
                                bit_sent<=5'b00000;
                        else if (clk1x_enable)
                                bit_sent<=bit_sent+1;
                end
//encode the data to manchester code
// assign data_out=(clk1x_enable & (data[16]^clk1x));
endmodule


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