control.rpt

语音信箱控制管理系统的设计与实现: 模拟语音信箱的功能有:记录语音,收阅与发送语音,擦除语音,


Device-Specific Information:                            d:\control\control.rpt
control

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC22 ADDRESS
        | +------------- LC23 ERASE
        | | +----------- LC21 PLAY
        | | | +--------- LC17 RECORDS
        | | | | +------- LC20 SAVE
        | | | | | +----- LC19 CURRENT_STATE2
        | | | | | | +--- LC18 CURRENT_STATE1
        | | | | | | | +- LC24 CURRENT_STATE0
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * * * * * * * * | - * | <-- RECORDS
LC19 -> * * * * * * * * | - * | <-- CURRENT_STATE2
LC18 -> * * * * * * * * | - * | <-- CURRENT_STATE1
LC24 -> * * * * * * * * | - * | <-- CURRENT_STATE0

Pin
43   -> - - - - - - - - | - - | <-- CLK
5    -> - - - * - * * * | - * | <-- KEY0
6    -> - - - * - * * * | - * | <-- KEY1
7    -> - - - * - * * * | - * | <-- KEY2
4    -> - - - * - * * * | - * | <-- KEY3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\control\control.rpt
control

** EQUATIONS **

CLK      : INPUT;
KEY0     : INPUT;
KEY1     : INPUT;
KEY2     : INPUT;
KEY3     : INPUT;

-- Node name is 'ADDRESS' 
-- Equation name is 'ADDRESS', location is LC022, type is output.
 ADDRESS = LCELL( _EQ001 $  GND);
  _EQ001 = !CURRENT_STATE0 &  CURRENT_STATE1 &  CURRENT_STATE2 & !RECORDS;

-- Node name is ':14' = 'CURRENT_STATE0' 
-- Equation name is 'CURRENT_STATE0', location is LC024, type is buried.
CURRENT_STATE0 = DFFE( _EQ002 $  VCC, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ002 =  CURRENT_STATE1 &  CURRENT_STATE2 & !KEY0 & !KEY1 &  KEY2 & !KEY3 & 
             !RECORDS
         #  CURRENT_STATE0 & !CURRENT_STATE1 & !KEY0 & !KEY2 & !RECORDS & 
              _X001
         # !CURRENT_STATE0 &  CURRENT_STATE1 &  CURRENT_STATE2 & !RECORDS & 
              _X002
         # !CURRENT_STATE0 & !CURRENT_STATE1 & !CURRENT_STATE2 & !RECORDS & 
              _X003
         #  CURRENT_STATE0 & !CURRENT_STATE1 &  CURRENT_STATE2 & !RECORDS;
  _X001  = EXP(!KEY1 &  KEY3);
  _X002  = EXP(!KEY0 &  KEY1 & !KEY2 &  KEY3);
  _X003  = EXP(!KEY1 & !KEY2 & !KEY3);

-- Node name is ':13' = 'CURRENT_STATE1' 
-- Equation name is 'CURRENT_STATE1', location is LC018, type is buried.
CURRENT_STATE1 = DFFE( _EQ003 $  CURRENT_STATE2, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ003 =  CURRENT_STATE0 &  CURRENT_STATE1 &  CURRENT_STATE2 & !KEY0 & 
             !KEY1 &  KEY2 & !KEY3
         #  CURRENT_STATE0 & !CURRENT_STATE1 & !CURRENT_STATE2 & !KEY1 & 
             !KEY2 & !KEY3 & !RECORDS
         # !CURRENT_STATE0 & !CURRENT_STATE1 &  CURRENT_STATE2
         #  CURRENT_STATE2 &  RECORDS;

-- Node name is ':12' = 'CURRENT_STATE2' 
-- Equation name is 'CURRENT_STATE2', location is LC019, type is buried.
CURRENT_STATE2 = DFFE( _EQ004 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ004 = !CURRENT_STATE0 & !CURRENT_STATE1 & !CURRENT_STATE2 &  KEY0 & 
             !KEY1 & !KEY2 & !KEY3 & !RECORDS
         #  CURRENT_STATE0 & !CURRENT_STATE1 & !KEY0 &  KEY1 & !KEY2 & !KEY3 & 
             !RECORDS
         # !KEY0 &  KEY1 & !KEY2 &  KEY3 &  RECORDS &  _X004
         #  CURRENT_STATE1 &  CURRENT_STATE2 & !RECORDS &  _X005
         #  CURRENT_STATE0 & !CURRENT_STATE1 &  CURRENT_STATE2 & !RECORDS;
  _X004  = EXP(!CURRENT_STATE0 & !CURRENT_STATE1 & !CURRENT_STATE2);
  _X005  = EXP( CURRENT_STATE0 & !KEY0 & !KEY1 &  KEY2 & !KEY3);

-- Node name is 'ERASE' 
-- Equation name is 'ERASE', location is LC023, type is output.
 ERASE   = LCELL( _EQ005 $  GND);
  _EQ005 = !CURRENT_STATE0 & !CURRENT_STATE1 &  CURRENT_STATE2 & !RECORDS;

-- Node name is 'PLAY' 
-- Equation name is 'PLAY', location is LC021, type is output.
 PLAY    = LCELL( _EQ006 $  GND);
  _EQ006 = !CURRENT_STATE0 &  CURRENT_STATE1 & !CURRENT_STATE2 & !RECORDS;

-- Node name is 'RECORDS' = 'CURRENT_STATE3' 
-- Equation name is 'RECORDS', location is LC017, type is output.
 RECORDS = TFFE( _EQ007, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ007 =  CURRENT_STATE0 &  CURRENT_STATE1 &  CURRENT_STATE2 & !KEY0 & 
             !KEY1 &  KEY2 & !KEY3 & !RECORDS
         #  CURRENT_STATE2 & !KEY0 &  KEY1 & !KEY2 &  KEY3 &  RECORDS
         #  CURRENT_STATE1 & !KEY0 &  KEY1 & !KEY2 &  KEY3 &  RECORDS
         #  CURRENT_STATE0 & !KEY0 &  KEY1 & !KEY2 &  KEY3 &  RECORDS;

-- Node name is 'SAVE' 
-- Equation name is 'SAVE', location is LC020, type is output.
 SAVE    = LCELL( _EQ008 $  GND);
  _EQ008 =  CURRENT_STATE0 &  CURRENT_STATE1 & !CURRENT_STATE2 & !RECORDS;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                     d:\control\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,233K