delay.vhd

来自「用vhdl的状态机实现精确的1us的延时程序」· VHDL 代码 · 共 43 行

--用状态机完成的1000ns的精确延时程序；
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity delay is
	port(clk,reset:in std_logic;
	   	 clk_out:out std_logic);
end;
architecture behav of delay is 
type delay_state is(state_start,state_delay);
signal current_state,next_state:delay_state;
signal state_flag:std_logic;
signal clk_signal:std_logic:='1';
--signal clr:std_logic:='0';
begin
REG:PROCESS(reset,clk)-- 时序逻辑进程
BEGIN
IF reset = '1' THEN
current_state <= state_start;-- 异步复位
ELSIF clk='1' AND clk'EVENT THEN
current_state <= next_state; -- 当测到时钟上升沿时转换至下一状态
END IF;
END PROCESS; -- 由信号current_state将当前状态值带出此进程，进入进程COM
process(clk,reset,current_state)
variable delay_count:integer range 0 to 2000;
  begin
  IF reset = '1' THEN
    delay_count:=0;
  elsif clk'event and clk='1' then
   case current_state is
     when state_start=> next_state<=state_delay;
     when state_delay=> delay_count:=delay_count+1;
				       if(delay_count<100) then 
		 clk_out<=state_flag;		          state_flag<='0';
				         else
				          state_flag<='1';
				       end if;
   end case;
  end if;
end process;

end behav;