uart.smp_dump.txt

基于FPGA的UART实现 用VHDL编程

State Machine - |UART|rxd:inst|state
Name state.r_stop state.r_sample state.r_wait state.r_center state.r_start 
state.r_start 0 0 0 0 0 
state.r_center 0 0 0 1 1 
state.r_wait 0 0 1 0 1 
state.r_sample 0 1 0 0 1 
state.r_stop 1 0 0 0 1 

State Machine - |UART|txd:inst1|state
Name state.x_stop state.x_shift state.x_wait state.x_start state.x_idle 
state.x_idle 0 0 0 0 0 
state.x_start 0 0 0 1 1 
state.x_wait 0 0 1 0 1 
state.x_shift 0 1 0 0 1 
state.x_stop 1 0 0 0 1