uart.fit.summary

基于FPGA的UART实现 用VHDL编程

Fitter Status : Successful - Fri Aug 10 08:20:18 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : UART
Top-level Entity Name : UART
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 220 / 2,910 ( 8 % )
Total pins : 4 / 104 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )