i2c_timesim.vhd

I2C程序

  signal i2c_ctrl_mbdr_i2c_3_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_3_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_3_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_3_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_3_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_3_MC_D2 : STD_LOGIC; 
  signal data_bus_4_MC_Q : STD_LOGIC; 
  signal data_bus_4_MC_OE : STD_LOGIC; 
  signal data_bus_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_4_MC_D : STD_LOGIC; 
  signal data_bus_4_MC_D1 : STD_LOGIC; 
  signal data_bus_4_MC_UIM : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_4_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_4_MC_D2 : STD_LOGIC; 
  signal data_bus_4_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_4_MC_D2 : STD_LOGIC; 
  signal data_bus_5_MC_Q : STD_LOGIC; 
  signal data_bus_5_MC_OE : STD_LOGIC; 
  signal data_bus_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_5_MC_D : STD_LOGIC; 
  signal data_bus_5_MC_D1 : STD_LOGIC; 
  signal data_bus_5_MC_UIM : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_5_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_5_MC_D2 : STD_LOGIC; 
  signal data_bus_5_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_5_MC_D2 : STD_LOGIC; 
  signal data_bus_6_MC_Q : STD_LOGIC; 
  signal data_bus_6_MC_OE : STD_LOGIC; 
  signal data_bus_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_6_MC_D : STD_LOGIC; 
  signal data_bus_6_MC_D1 : STD_LOGIC; 
  signal data_bus_6_MC_UIM : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_6_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_6_MC_D2 : STD_LOGIC; 
  signal data_bus_6_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_6_MC_D2 : STD_LOGIC; 
  signal data_bus_7_MC_Q : STD_LOGIC; 
  signal data_bus_7_MC_OE : STD_LOGIC; 
  signal data_bus_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_7_MC_D : STD_LOGIC; 
  signal data_bus_7_MC_D1 : STD_LOGIC; 
  signal data_bus_7_MC_UIM : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_7_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_7_MC_D2 : STD_LOGIC; 
  signal data_bus_7_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_7_MC_D2 : STD_LOGIC; 
  signal dtack_MC_Q : STD_LOGIC; 
  signal dtack_MC_OE : STD_LOGIC; 
  signal dtack_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal dtack_MC_D : STD_LOGIC; 
  signal dtack_MC_D1_PT_0 : STD_LOGIC; 
  signal dtack_MC_D1 : STD_LOGIC; 
  signal dtack_MC_D2 : STD_LOGIC; 
  signal dtack_MC_BUFOE_OUT : STD_LOGIC; 
  signal irq_MC_Q : STD_LOGIC; 
  signal irq_MC_OE : STD_LOGIC; 
  signal irq_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal irq_MC_D : STD_LOGIC; 
  signal irq_MC_D1 : STD_LOGIC; 
  signal irq_MC_D2 : STD_LOGIC; 
  signal irq_MC_BUFOE_OUT : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_1_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_2_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR1_ctinst_4_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR5_ctinst_7_OUT : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_i2c_header_en_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_i2c_header_en_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR3_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR6_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_men_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_men_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_men_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_men_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_564_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR2_ctinst_1_OUT : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_prs_state_fft2_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_prs_state_fft2_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_prs_state_fft2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_prs_state_fft1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_prs_state_fft1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_prs_state_fft1_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_prs_state_fft1_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_address_match_MC_D1_PT_0_IN17 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR8_ctinst_0_OUT : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_ds_int_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_data_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_data_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_data_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_data_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_stat_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_stat_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_stat_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_stat_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_cntrl_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_cntrl_en_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_cntrl_en_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_cntrl_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_cntrl_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_addr_en_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_addr_en_MC_D1_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_addr_en_MC_D1_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_addr_en_MC_D1_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR9_ctinst_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR9_ctinst_1_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR9_ctinst_2_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR9_ctinst_4_OUT : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR7_ctinst_4_OUT : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_n0171_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_mif_bit_reset_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_mif_bit_reset_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_mif_bit_reset_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_mcf_MC_D1_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_bit_cnt_0_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd1_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_state_ffd2_MC_D2_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_arb_lost_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_msta_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_msta_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_uc_ctrl_msta_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_msta_rst_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_msta_rst_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_msta_rst_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_msta_rst_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_msta_rst_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_msta_rst_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_msta_rst_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_683_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_ctrl_sda_out_reg_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_i2c_c