i2c_timesim.vhd

I2C程序

  signal i2c_ctrl_i2c_header_2_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_2_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_2_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_2_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_2_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_3_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_3_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_3_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_3_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_3_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_3_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_4_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_4_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_4_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_4_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_4_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_4_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_5_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_5_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_5_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_5_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_5_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_5_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_6_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_6_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_6_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_6_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_6_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_6_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_7_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_7_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_7_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_7_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_7_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_7_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_n0170 : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_CE_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mal_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mal_bit_reset_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_d1 : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D2_PT_4 : STD_LOGIC; 
  signal i2c_ctrl_n0170_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_d1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_d1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_d1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_d1_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_d1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_d1_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_D : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_maas_MC_D_TFF : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_mbcr_wr_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_mif_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mif_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mif_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mien_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mien_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_detect_stop_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_detect_stop_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_detect_stop_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_scl_out_reg_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_scl_out_reg_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_scl_out_reg_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_scl_out_reg_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_n0096_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_n0096_MC_D : STD_LOGIC; 
  signal i2c_ctrl_n0096_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_n0096_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_n0096_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_slave_sda : STD_LOGIC; 
  signal i2c_ctrl_n0096_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_n0096_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_slave_sda_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_slave_sda_MC_D : STD_LOGIC; 
  signal i2c_ctrl_slave_sda_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_slave_sda_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_slave_sda_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_slave_sda_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_slave_sda_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_n0073_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_n0073_MC_D : STD_LOGIC; 
  signal i2c_ctrl_n0073_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_n0073_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_n0073_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_n0073_MC_D2 : STD_LOGIC; 
  signal data_bus_0_MC_D1 : STD_LOGIC; 
  signal data_bus_0_MC_UIM : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_rxak : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_0_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_0_MC_D2 : STD_LOGIC; 
  signal data_bus_0_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_0_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_rxak_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_rxak_MC_D : STD_LOGIC; 
  signal i2c_ctrl_rxak_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_rxak_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_rxak_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_madr_0_MC_D2 : STD_LOGIC; 
  signal data_bus_1_MC_Q : STD_LOGIC; 
  signal data_bus_1_MC_OE : STD_LOGIC; 
  signal data_bus_1_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_1_MC_D : STD_LOGIC; 
  signal data_bus_1_MC_D1 : STD_LOGIC; 
  signal data_bus_1_MC_UIM : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_1_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_1_MC_D2 : STD_LOGIC; 
  signal data_bus_1_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_1_MC_D2 : STD_LOGIC; 
  signal data_bus_2_MC_Q : STD_LOGIC; 
  signal data_bus_2_MC_OE : STD_LOGIC; 
  signal data_bus_2_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_2_MC_D : STD_LOGIC; 
  signal data_bus_2_MC_D1 : STD_LOGIC; 
  signal data_bus_2_MC_UIM : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_srw : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_2_MC_D2_PT_4 : STD_LOGIC; 
  signal data_bus_2_MC_D2 : STD_LOGIC; 
  signal data_bus_2_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_D : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_2_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_D : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_CE : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_CE_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_srw_MC_D2 : STD_LOGIC; 
  signal data_bus_3_MC_Q : STD_LOGIC; 
  signal data_bus_3_MC_OE : STD_LOGIC; 
  signal data_bus_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal data_bus_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_3_MC_D : STD_LOGIC; 
  signal data_bus_3_MC_D1 : STD_LOGIC; 
  signal data_bus_3_MC_UIM : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_1 : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_2 : STD_LOGIC; 
  signal data_bus_3_MC_D2_PT_3 : STD_LOGIC; 
  signal data_bus_3_MC_D2 : STD_LOGIC; 
  signal data_bus_3_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_3_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mbdr_i2c_3_MC_R_OR_PRLD : STD_LOGIC;