i2c_timesim.vhd

I2C程序

  signal i2c_ctrl_gen_stop_MC_D : STD_LOGIC; 
  signal i2c_ctrl_gen_stop_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_gen_stop_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_gen_stop_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_gen_stop_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_D : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_sm_stop_MC_D_TFF : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_D1 : STD_LOGIC; 
  signal N_PZ_668 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_1_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_668_MC_Q : STD_LOGIC; 
  signal N_PZ_668_MC_D : STD_LOGIC; 
  signal N_PZ_668_MC_D1 : STD_LOGIC; 
  signal N_PZ_668_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_668_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_668_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_668_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_D : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_2_MC_D_TFF : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_D : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_n0159_MC_D_TFF : STD_LOGIC; 
  signal i2c_ctrl_master_sda_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_master_sda_MC_D : STD_LOGIC; 
  signal i2c_ctrl_master_sda_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_txak : STD_LOGIC; 
  signal i2c_ctrl_master_sda_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_out : STD_LOGIC; 
  signal i2c_ctrl_master_sda_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_master_sda_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_master_sda_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_txak_MC_Q : STD_LOGIC; 
  signal uc_ctrl_txak_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D1 : STD_LOGIC; 
  signal data_bus_3_II_UIM : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_txak_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_out_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D2_PT_4 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_ld_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_4_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mtx_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_0_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_0_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_0_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_0_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_0_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D1 : STD_LOGIC; 
  signal N_PZ_559 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_7_MC_D2 : STD_LOGIC; 
  signal N_PZ_559_MC_Q : STD_LOGIC; 
  signal N_PZ_559_MC_D : STD_LOGIC; 
  signal N_PZ_559_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_559_MC_D1 : STD_LOGIC; 
  signal N_PZ_559_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_en_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_6_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D1 : STD_LOGIC; 
  signal data_bus_6_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_6_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_5_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_5_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_4_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_4_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_3_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_3_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_2_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_2_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_1_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D1 : STD_LOGIC; 
  signal data_bus_1_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_1_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_D : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_shift_reg_0_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_Q : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_0_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mbdr_micro_0_MC_D2 : STD_LOGIC; 
  signal n7280_MC_Q : STD_LOGIC; 
  signal n7280_MC_D : STD_LOGIC; 
  signal n7280_MC_D1 : STD_LOGIC; 
  signal n7280_MC_D2_PT_0 : STD_LOGIC; 
  signal n7280_MC_D2_PT_1 : STD_LOGIC; 
  signal n7280_MC_D2_PT_2 : STD_LOGIC; 
  signal n7280_MC_D2_PT_3 : STD_LOGIC; 
  signal n7280_MC_D2_PT_4 : STD_LOGIC; 
  signal n7280_MC_D2_PT_5 : STD_LOGIC; 
  signal n7280_MC_D2_PT_6 : STD_LOGIC; 
  signal n7280_MC_D2_PT_7 : STD_LOGIC; 
  signal n7280_MC_D2_PT_8 : STD_LOGIC; 
  signal n7280_MC_D2_PT_9 : STD_LOGIC; 
  signal n7280_MC_D2_PT_10 : STD_LOGIC; 
  signal n7280_MC_D2_PT_11 : STD_LOGIC; 
  signal n7280_MC_D2_PT_12 : STD_LOGIC; 
  signal n7280_MC_D2_PT_13 : STD_LOGIC; 
  signal n7280_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_1_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_1_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_Q : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D1 : STD_LOGIC; 
  signal N_PZ_560 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_madr_1_MC_D2 : STD_LOGIC; 
  signal N_PZ_560_MC_Q : STD_LOGIC; 
  signal N_PZ_560_MC_D : STD_LOGIC; 
  signal N_PZ_560_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_560_MC_D1 : STD_LOGIC; 
  signal N_PZ_560_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_2_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_2_MC_R_OR_PRLD : STD_LOGIC;