i2c_timesim.vhd

I2C程序

  signal uc_ctrl_mif_bit_reset_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_2_II_UIM : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_D2 : STD_LOGIC; 
  signal mcf_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal mcf_MC_Q : STD_LOGIC; 
  signal mcf_MC_R_OR_PRLD : STD_LOGIC; 
  signal mcf_MC_D : STD_LOGIC; 
  signal i2c_ctrl_n0159 : STD_LOGIC; 
  signal mcf_MC_D1_PT_0 : STD_LOGIC; 
  signal mcf_MC_D1 : STD_LOGIC; 
  signal mcf_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_D : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_bit_cnt_0_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_arb_lost : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_sda_in : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D2_PT_3 : STD_LOGIC; 
  signal n7280 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D2_PT_4 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_mtx : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D2_PT_4 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_D : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_683 : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1 : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_arb_lost_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_master_slave_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_master_slave_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_master_slave_MC_D : STD_LOGIC; 
  signal uc_ctrl_msta : STD_LOGIC; 
  signal i2c_ctrl_master_slave_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_master_slave_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_master_slave_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_msta_MC_Q : STD_LOGIC; 
  signal uc_ctrl_msta_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_msta_rst : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D2_PT_0 : STD_LOGIC; 
  signal data_bus_5_II_UIM : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_msta_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_D : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_msta_rst_MC_D2 : STD_LOGIC; 
  signal N_PZ_683_MC_Q : STD_LOGIC; 
  signal N_PZ_683_MC_D : STD_LOGIC; 
  signal N_PZ_683_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_scl_in : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_d1 : STD_LOGIC; 
  signal N_PZ_683_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_683_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_683_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_683_MC_D2_PT_3 : STD_LOGIC; 
  signal N_PZ_683_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_sda_in_MC_D : STD_LOGIC; 
  signal i2c_ctrl_sda_in_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_sda_in_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_sda_in_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_sda_in_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal i2c_ctrl_sda_in_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_sda_in_MC_OE : STD_LOGIC; 
  signal i2c_ctrl_scl_in_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_scl_in_MC_D : STD_LOGIC; 
  signal i2c_ctrl_scl_in_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_scl_in_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_scl_in_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_d1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_d1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_d1_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_d1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_d1_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_4 : STD_LOGIC; 
  signal uc_ctrl_rsta : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_5 : STD_LOGIC; 
  signal i2c_ctrl_n0153 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_6 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_7 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_8 : STD_LOGIC; 
  signal i2c_ctrl_gen_stop : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_9 : STD_LOGIC; 
  signal i2c_ctrl_sm_stop : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_10 : STD_LOGIC; 
  signal i2c_ctrl_master_sda : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2_PT_11 : STD_LOGIC; 
  signal i2c_ctrl_sda_out_reg_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft2_MC_D_TFF : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_4 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_5 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_6 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2_PT_7 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft3_MC_D_TFF : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_gen_start : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_scl_state_fft1_MC_D_TFF : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_MC_D : STD_LOGIC; 
  signal FOOBAR4_ctinst_4 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_gen_start_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_gen_start_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_gen_start_MC_D : STD_LOGIC; 
  signal i2c_ctrl_gen_start_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_gen_start_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_msta_d1 : STD_LOGIC; 
  signal i2c_ctrl_gen_start_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_gen_start_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_msta_d1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_msta_d1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_msta_d1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_msta_d1_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_msta_d1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_msta_d1_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D1 : STD_LOGIC; 
  signal N_PZ_667 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_0_MC_D_TFF : STD_LOGIC; 
  signal N_PZ_667_MC_Q : STD_LOGIC; 
  signal N_PZ_667_MC_D : STD_LOGIC; 
  signal N_PZ_667_MC_D1 : STD_LOGIC; 
  signal N_PZ_667_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_667_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_667_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_667_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_D : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_662 : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_n0153_MC_D_TFF : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_1_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_1_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_1_MC_D : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_1_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_1_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_1_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_1_MC_D2 : STD_LOGIC; 
  signal N_PZ_662_MC_Q : STD_LOGIC; 
  signal N_PZ_662_MC_D : STD_LOGIC; 
  signal N_PZ_662_MC_D1 : STD_LOGIC; 
  signal N_PZ_662_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_662_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_662_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D2_PT_3 : STD_LOGIC; 
  signal i2c_ctrl_clk_cnt_2_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_Q : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2_PT_3 : STD_LOGIC; 
  signal uc_ctrl_rsta_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_D : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_D2_PT_2 : STD_LOGIC; 
  signal i2c_ctrl_stop_scl_reg_MC_D2 : STD_LOGIC; 
  signal N_PZ_641_MC_Q : STD_LOGIC; 
  signal N_PZ_641_MC_D : STD_LOGIC; 
  signal N_PZ_641_MC_D1 : STD_LOGIC; 
  signal N_PZ_641_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_641_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_641_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_gen_stop_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_gen_stop_MC_R_OR_PRLD : STD_LOGIC;