i2c_timesim.vhd

I2C程序

-- Xilinx Vhdl produced by program ngd2vhdl F.26
-- Command: -rpw 100 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log i2c.nga i2c_timesim.vhd 
-- Input file: i2c.nga
-- Output file: i2c_timesim.vhd
-- Design name: i2c
-- Xilinx: C:/Xilinx_webpack_51
-- # of Entities: 1
-- Device: XCR3256XL-7-TQ144

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity i2c is
  port (
    clk : in STD_LOGIC := 'X'; 
    r_w : in STD_LOGIC := 'X'; 
    as : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    sda : inout STD_LOGIC; 
    scl : inout STD_LOGIC; 
    dtack : out STD_LOGIC; 
    irq : out STD_LOGIC; 
    mcf : out STD_LOGIC; 
    ds : in STD_LOGIC := 'X'; 
    addr_bus : in STD_LOGIC_VECTOR ( 23 downto 0 ); 
    data_bus : inout STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end i2c;

architecture Structure of i2c is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal data_bus_0_MC_Q : STD_LOGIC; 
  signal data_bus_0_MC_OE : STD_LOGIC; 
  signal data_bus_0_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal FOOBAR1_ctinst_2 : STD_LOGIC; 
  signal data_bus_0_MC_R_OR_PRLD : STD_LOGIC; 
  signal data_bus_0_MC_D : STD_LOGIC; 
  signal clk_II_FCLK : STD_LOGIC; 
  signal i2c_ctrl_scl_out_reg : STD_LOGIC; 
  signal FOOBAR1_ctinst_0 : STD_LOGIC; 
  signal i2c_ctrl_n0096 : STD_LOGIC; 
  signal FOOBAR1_ctinst_1 : STD_LOGIC; 
  signal reset_II_UIM : STD_LOGIC; 
  signal i2c_ctrl_n0073 : STD_LOGIC; 
  signal FOOBAR1_ctinst_3 : STD_LOGIC; 
  signal i2c_ctrl_bus_busy : STD_LOGIC; 
  signal FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal sda_II_UIM : STD_LOGIC; 
  signal FOOBAR1_ctinst_5 : STD_LOGIC; 
  signal scl_II_UIM : STD_LOGIC; 
  signal FOOBAR1_ctinst_7 : STD_LOGIC; 
  signal i2c_ctrl_scl_out_reg_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_scl_out_reg_MC_D : STD_LOGIC; 
  signal FOOBAR5_ctinst_7 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en : STD_LOGIC; 
  signal FOOBAR5_ctinst_4 : STD_LOGIC; 
  signal uc_ctrl_men : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en_MC_D : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_detect_start : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd1 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd2 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en_MC_D2_PT_1 : STD_LOGIC; 
  signal i2c_ctrl_i2c_header_en_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_D : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_BUFOE_OUT : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_OE : STD_LOGIC; 
  signal i2c_ctrl_detect_start_MC_R_OR_PRLD : STD_LOGIC; 
  signal FOOBAR1_ctinst_5_tsimcreated_inv_Q : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_Q : STD_LOGIC; 
  signal FOOBAR3_ctinst_0 : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_state_ffd3_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_7_tsimcreated_inv_Q : STD_LOGIC; 
  signal i2c_ctrl_detect_stop : STD_LOGIC; 
  signal uc_ctrl_men_MC_Q : STD_LOGIC; 
  signal FOOBAR6_ctinst_0 : STD_LOGIC; 
  signal uc_ctrl_men_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_men_MC_D : STD_LOGIC; 
  signal uc_ctrl_men_MC_D1 : STD_LOGIC; 
  signal N_PZ_564 : STD_LOGIC; 
  signal data_bus_7_II_UIM : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_men_MC_D2 : STD_LOGIC; 
  signal N_PZ_564_MC_Q : STD_LOGIC; 
  signal N_PZ_564_MC_D : STD_LOGIC; 
  signal r_w_II_UIM : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1 : STD_LOGIC; 
  signal uc_ctrl_cntrl_en : STD_LOGIC; 
  signal N_PZ_564_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_564_MC_D1 : STD_LOGIC; 
  signal N_PZ_564_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_Q : STD_LOGIC; 
  signal FOOBAR2_ctinst_1 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_D : STD_LOGIC; 
  signal FOOBAR2_ctinst_0 : STD_LOGIC; 
  signal FOOBAR2_ctinst_7 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_as_int_d1 : STD_LOGIC; 
  signal uc_ctrl_ds_int : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_address_match : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft2_MC_D_TFF : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_Q : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_D : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_D2_PT_1 : STD_LOGIC; 
  signal as_II_UIM : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_prs_state_fft1_MC_D_TFF : STD_LOGIC; 
  signal uc_ctrl_address_match_MC_Q : STD_LOGIC; 
  signal uc_ctrl_address_match_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_address_match_MC_D : STD_LOGIC; 
  signal addr_bus_10_II_UIM : STD_LOGIC; 
  signal addr_bus_11_II_UIM : STD_LOGIC; 
  signal addr_bus_12_II_UIM : STD_LOGIC; 
  signal addr_bus_13_II_UIM : STD_LOGIC; 
  signal addr_bus_14_II_UIM : STD_LOGIC; 
  signal addr_bus_15_II_UIM : STD_LOGIC; 
  signal addr_bus_16_II_UIM : STD_LOGIC; 
  signal addr_bus_17_II_UIM : STD_LOGIC; 
  signal addr_bus_18_II_UIM : STD_LOGIC; 
  signal addr_bus_19_II_UIM : STD_LOGIC; 
  signal addr_bus_20_II_UIM : STD_LOGIC; 
  signal addr_bus_21_II_UIM : STD_LOGIC; 
  signal addr_bus_22_II_UIM : STD_LOGIC; 
  signal addr_bus_23_II_UIM : STD_LOGIC; 
  signal addr_bus_8_II_UIM : STD_LOGIC; 
  signal addr_bus_9_II_UIM : STD_LOGIC; 
  signal uc_ctrl_address_match_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_address_match_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_address_match_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_as_int_d1_MC_Q : STD_LOGIC; 
  signal uc_ctrl_as_int_d1_MC_D : STD_LOGIC; 
  signal FOOBAR8_ctinst_0 : STD_LOGIC; 
  signal uc_ctrl_as_int : STD_LOGIC; 
  signal uc_ctrl_as_int_d1_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_as_int_d1_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_as_int_d1_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_as_int_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_D : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_COMB : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_D2_PT_0 : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_D2_PT_1 : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_D2_PT_2 : STD_LOGIC; 
  signal uc_ctrl_data_en : STD_LOGIC; 
  signal uc_ctrl_stat_en : STD_LOGIC; 
  signal uc_ctrl_addr_en : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_D2_PT_3 : STD_LOGIC; 
  signal uc_ctrl_ds_int_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D : STD_LOGIC; 
  signal addr_bus_0_II_UIM : STD_LOGIC; 
  signal addr_bus_1_II_UIM : STD_LOGIC; 
  signal addr_bus_2_II_UIM : STD_LOGIC; 
  signal addr_bus_3_II_UIM : STD_LOGIC; 
  signal addr_bus_4_II_UIM : STD_LOGIC; 
  signal addr_bus_5_II_UIM : STD_LOGIC; 
  signal addr_bus_6_II_UIM : STD_LOGIC; 
  signal addr_bus_7_II_UIM : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_data_en_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_stat_en_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_cntrl_en_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_Q : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_R_OR_PRLD : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D1_PT_0 : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D1 : STD_LOGIC; 
  signal uc_ctrl_addr_en_MC_D2 : STD_LOGIC; 
  signal i2c_ctrl_detect_stop_MC_Q : STD_LOGIC; 
  signal FOOBAR9_ctinst_1 : STD_LOGIC; 
  signal i2c_ctrl_detect_stop_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_detect_stop_MC_D : STD_LOGIC; 
  signal FOOBAR9_ctinst_5 : STD_LOGIC; 
  signal i2c_ctrl_mif : STD_LOGIC; 
  signal uc_ctrl_mien : STD_LOGIC; 
  signal FOOBAR9_ctinst_0 : STD_LOGIC; 
  signal FOOBAR9_ctinst_2 : STD_LOGIC; 
  signal N_PZ_641 : STD_LOGIC; 
  signal FOOBAR9_ctinst_4 : STD_LOGIC; 
  signal i2c_ctrl_mif_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_mif_MC_R_OR_PRLD : STD_LOGIC; 
  signal i2c_ctrl_mif_MC_D : STD_LOGIC; 
  signal FOOBAR7_ctinst_4 : STD_LOGIC; 
  signal i2c_ctrl_n0171 : STD_LOGIC; 
  signal i2c_ctrl_n0171_MC_Q : STD_LOGIC; 
  signal i2c_ctrl_n0171_MC_D : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset : STD_LOGIC; 
  signal mcf_MC_UIM : STD_LOGIC; 
  signal i2c_ctrl_mal : STD_LOGIC; 
  signal i2c_ctrl_n0171_MC_D1_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_n0171_MC_D1 : STD_LOGIC; 
  signal i2c_ctrl_master_slave : STD_LOGIC; 
  signal i2c_ctrl_maas : STD_LOGIC; 
  signal i2c_ctrl_n0171_MC_D2_PT_0 : STD_LOGIC; 
  signal i2c_ctrl_n0171_MC_D2 : STD_LOGIC; 
  signal uc_ctrl_mif_bit_reset_MC_Q : STD_LOGIC;