lab_6_1.vhd

用VHDL描述的74ls163,模拟实现其时序逻辑功能

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab_6_1 is
    Port ( clock : in std_logic;
           clear : in std_logic;
           load : in std_logic;
           p : in std_logic;
           t : in std_logic;
           a : in std_logic;
           b : in std_logic;
           c : in std_logic;
           d : in std_logic;
           qa : out std_logic;
           qb : out std_logic;
           qc : out std_logic;
           qd : out std_logic;
           rco : out std_logic);
end lab_6_1;

architecture Behavioral of lab_6_1 is

	signal q:std_logic_vector(3 downto 0);

begin
	process(clock,clear,p,t)
	begin
		if (clock'event and clock='1') then
			if (clear='0') then q<="0000";
				elsif load='0' then 
					q<=d&c&b&a;
				elsif (p='1' and t='1') then
					q<=q+1;
			end if;
		end if;
	end process;
	qa<=q(0);
	qb<=q(1);
	qc<=q(2);
	qd<=q(3);
	rco<='1' when q="1111" else '0';
end Behavioral;