division_a.tan.rpt

正交方波信号的四细分功能

; N/A   ; None         ; -0.199 ns  ; pb   ; db[1]~reg0     ; clk      ;
; N/A   ; None         ; -0.199 ns  ; pb   ; db[2]~reg0     ; clk      ;
; N/A   ; None         ; -0.199 ns  ; pb   ; db[3]~reg0     ; clk      ;
; N/A   ; None         ; -0.199 ns  ; pb   ; db[4]~reg0     ; clk      ;
; N/A   ; None         ; -0.199 ns  ; pb   ; db[5]~reg0     ; clk      ;
; N/A   ; None         ; -0.199 ns  ; pb   ; db[6]~reg0     ; clk      ;
; N/A   ; None         ; -0.199 ns  ; pb   ; db[7]~reg0     ; clk      ;
+-------+--------------+------------+------+----------------+----------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From           ; To        ; From Clock ;
+-------+--------------+------------+----------------+-----------+------------+
; N/A   ; None         ; 9.407 ns   ; db[1]~reg0     ; db[1]     ; clk        ;
; N/A   ; None         ; 9.036 ns   ; db[7]~reg0     ; db[7]     ; clk        ;
; N/A   ; None         ; 8.868 ns   ; db[5]~reg0     ; db[5]     ; clk        ;
; N/A   ; None         ; 8.861 ns   ; db[6]~reg0     ; db[6]     ; clk        ;
; N/A   ; None         ; 8.793 ns   ; db[4]~reg0     ; db[4]     ; clk        ;
; N/A   ; None         ; 8.712 ns   ; db[0]~reg0     ; db[0]     ; clk        ;
; N/A   ; None         ; 8.653 ns   ; db[3]~reg0     ; db[3]     ; clk        ;
; N/A   ; None         ; 8.518 ns   ; db[2]~reg0     ; db[2]     ; clk        ;
; N/A   ; None         ; 6.226 ns   ; pbreg~reg0     ; pbreg     ; clk        ;
; N/A   ; None         ; 5.724 ns   ; beginning~reg0 ; beginning ; clk        ;
; N/A   ; None         ; 5.354 ns   ; pareg~reg0     ; pareg     ; clk        ;
+-------+--------------+------------+----------------+-----------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+------+----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To             ; To Clock ;
+---------------+-------------+-----------+------+----------------+----------+
; N/A           ; None        ; 0.438 ns  ; pb   ; db[0]~reg0     ; clk      ;
; N/A           ; None        ; 0.438 ns  ; pb   ; db[1]~reg0     ; clk      ;
; N/A           ; None        ; 0.438 ns  ; pb   ; db[2]~reg0     ; clk      ;
; N/A           ; None        ; 0.438 ns  ; pb   ; db[3]~reg0     ; clk      ;
; N/A           ; None        ; 0.438 ns  ; pb   ; db[4]~reg0     ; clk      ;
; N/A           ; None        ; 0.438 ns  ; pb   ; db[5]~reg0     ; clk      ;
; N/A           ; None        ; 0.438 ns  ; pb   ; db[6]~reg0     ; clk      ;
; N/A           ; None        ; 0.438 ns  ; pb   ; db[7]~reg0     ; clk      ;
; N/A           ; None        ; -0.047 ns ; pa   ; pareg~reg0     ; clk      ;
; N/A           ; None        ; -0.321 ns ; pa   ; beginning~reg0 ; clk      ;
; N/A           ; None        ; -2.337 ns ; pb   ; pbreg~reg0     ; clk      ;
; N/A           ; None        ; -2.701 ns ; pb   ; beginning~reg0 ; clk      ;
+---------------+-------------+-----------+------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Tue Apr 15 10:18:45 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off division_A -c division_A --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "beginning~reg0" as buffer
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "db[0]~reg0" and destination register "db[7]~reg0"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.952 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db[0]~reg0'
            Info: 2: + IC(0.211 ns) + CELL(0.309 ns) = 0.520 ns; Loc. = LCCOMB_X5_Y10_N16; Fanout = 2; COMB Node = 'Add0~130'
            Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.555 ns; Loc. = LCCOMB_X5_Y10_N18; Fanout = 2; COMB Node = 'Add0~134'
            Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.590 ns; Loc. = LCCOMB_X5_Y10_N20; Fanout = 2; COMB Node = 'Add0~138'
            Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.625 ns; Loc. = LCCOMB_X5_Y10_N22; Fanout = 2; COMB Node = 'Add0~142'
            Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 0.660 ns; Loc. = LCCOMB_X5_Y10_N24; Fanout = 2; COMB Node = 'Add0~146'
            Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 0.695 ns; Loc. = LCCOMB_X5_Y10_N26; Fanout = 2; COMB Node = 'Add0~150'
            Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 0.730 ns; Loc. = LCCOMB_X5_Y10_N28; Fanout = 1; COMB Node = 'Add0~154'
            Info: 9: + IC(0.000 ns) + CELL(0.125 ns) = 0.855 ns; Loc. = LCCOMB_X5_Y10_N30; Fanout = 1; COMB Node = 'Add0~157'
            Info: 10: + IC(0.000 ns) + CELL(0.097 ns) = 0.952 ns; Loc. = LCFF_X5_Y10_N31; Fanout = 2; REG Node = 'db[7]~reg0'
            Info: Total cell delay = 0.741 ns ( 77.84 % )
            Info: Total interconnect delay = 0.211 ns ( 22.16 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 5.670 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(0.886 ns) + CELL(0.712 ns) = 2.452 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'
                Info: 3: + IC(1.940 ns) + CELL(0.000 ns) = 4.392 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'beginning~reg0clkctrl'
                Info: 4: + IC(0.660 ns) + CELL(0.618 ns) = 5.670 ns; Loc. = LCFF_X5_Y10_N31; Fanout = 2; REG Node = 'db[7]~reg0'
                Info: Total cell delay = 2.184 ns ( 38.52 % )
                Info: Total interconnect delay = 3.486 ns ( 61.48 % )
            Info: - Longest clock path from clock "clk" to source register is 5.670 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(0.886 ns) + CELL(0.712 ns) = 2.452 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'
                Info: 3: + IC(1.940 ns) + CELL(0.000 ns) = 4.392 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'beginning~reg0clkctrl'
                Info: 4: + IC(0.660 ns) + CELL(0.618 ns) = 5.670 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db[0]~reg0'
                Info: Total cell delay = 2.184 ns ( 38.52 % )
                Info: Total interconnect delay = 3.486 ns ( 61.48 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "beginning~reg0" (data pin = "pb", clock pin = "clk") is 2.940 ns
    Info: + Longest pin to register delay is 5.208 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N19; Fanout = 10; PIN Node = 'pb'
        Info: 2: + IC(3.842 ns) + CELL(0.357 ns) = 5.053 ns; Loc. = LCCOMB_X6_Y10_N24; Fanout = 1; COMB Node = 'always0~2'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.208 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'
        Info: Total cell delay = 1.366 ns ( 26.23 % )
        Info: Total interconnect delay = 3.842 ns ( 73.77 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.358 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.886 ns) + CELL(0.618 ns) = 2.358 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'
        Info: Total cell delay = 1.472 ns ( 62.43 % )
        Info: Total interconnect delay = 0.886 ns ( 37.57 % )
Info: tco from clock "clk" to destination pin "db[1]" through register "db[1]~reg0" is 9.407 ns
    Info: + Longest clock path from clock "clk" to source register is 5.670 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.886 ns) + CELL(0.712 ns) = 2.452 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'
        Info: 3: + IC(1.940 ns) + CELL(0.000 ns) = 4.392 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'beginning~reg0clkctrl'
        Info: 4: + IC(0.660 ns) + CELL(0.618 ns) = 5.670 ns; Loc. = LCFF_X5_Y10_N19; Fanout = 3; REG Node = 'db[1]~reg0'
        Info: Total cell delay = 2.184 ns ( 38.52 % )
        Info: Total interconnect delay = 3.486 ns ( 61.48 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.643 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y10_N19; Fanout = 3; REG Node = 'db[1]~reg0'
        Info: 2: + IC(1.711 ns) + CELL(1.932 ns) = 3.643 ns; Loc. = PIN_G15; Fanout = 0; PIN Node = 'db[1]'
        Info: Total cell delay = 1.932 ns ( 53.03 % )
        Info: Total interconnect delay = 1.711 ns ( 46.97 % )
Info: th for register "db[0]~reg0" (data pin = "pb", clock pin = "clk") is 0.438 ns
    Info: + Longest clock path from clock "clk" to destination register is 5.670 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.886 ns) + CELL(0.712 ns) = 2.452 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'
        Info: 3: + IC(1.940 ns) + CELL(0.000 ns) = 4.392 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'beginning~reg0clkctrl'
        Info: 4: + IC(0.660 ns) + CELL(0.618 ns) = 5.670 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db[0]~reg0'
        Info: Total cell delay = 2.184 ns ( 38.52 % )
        Info: Total interconnect delay = 3.486 ns ( 61.48 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.381 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N19; Fanout = 10; PIN Node = 'pb'
        Info: 2: + IC(3.781 ns) + CELL(0.746 ns) = 5.381 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db[0]~reg0'
        Info: Total cell delay = 1.600 ns ( 29.73 % )
        Info: Total interconnect delay = 3.781 ns ( 70.27 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Tue Apr 15 10:18:48 2008
    Info: Elapsed time: 00:00:03