division_a.tan.qmsg

正交方波信号的四细分功能

{ "Info" "ITDB_TH_RESULT" "db\[0\]~reg0 pb clk 0.438 ns register " "Info: th for register \"db\[0\]~reg0\" (data pin = \"pb\", clock pin = \"clk\") is 0.438 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.670 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.712 ns) 2.452 ns beginning~reg0 2 REG LCFF_X6_Y10_N25 2 " "Info: 2: + IC(0.886 ns) + CELL(0.712 ns) = 2.452 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { clk beginning~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 12 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.940 ns) + CELL(0.000 ns) 4.392 ns beginning~reg0clkctrl 3 COMB CLKCTRL_G7 8 " "Info: 3: + IC(1.940 ns) + CELL(0.000 ns) = 4.392 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'beginning~reg0clkctrl'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.940 ns" { beginning~reg0 beginning~reg0clkctrl } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(0.618 ns) 5.670 ns db\[0\]~reg0 4 REG LCFF_X5_Y10_N15 3 " "Info: 4: + IC(0.660 ns) + CELL(0.618 ns) = 5.670 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db\[0\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { beginning~reg0clkctrl db[0]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.184 ns ( 38.52 % ) " "Info: Total cell delay = 2.184 ns ( 38.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.486 ns ( 61.48 % ) " "Info: Total interconnect delay = 3.486 ns ( 61.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.670 ns" { clk beginning~reg0 beginning~reg0clkctrl db[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.670 ns" { clk clk~combout beginning~reg0 beginning~reg0clkctrl db[0]~reg0 } { 0.000ns 0.000ns 0.886ns 1.940ns 0.660ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.381 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns pb 1 PIN PIN_N19 10 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N19; Fanout = 10; PIN Node = 'pb'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { pb } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.781 ns) + CELL(0.746 ns) 5.381 ns db\[0\]~reg0 2 REG LCFF_X5_Y10_N15 3 " "Info: 2: + IC(3.781 ns) + CELL(0.746 ns) = 5.381 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db\[0\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.527 ns" { pb db[0]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 29.73 % ) " "Info: Total cell delay = 1.600 ns ( 29.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.781 ns ( 70.27 % ) " "Info: Total interconnect delay = 3.781 ns ( 70.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.381 ns" { pb db[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.381 ns" { pb pb~combout db[0]~reg0 } { 0.000ns 0.000ns 3.781ns } { 0.000ns 0.854ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.670 ns" { clk beginning~reg0 beginning~reg0clkctrl db[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.670 ns" { clk clk~combout beginning~reg0 beginning~reg0clkctrl db[0]~reg0 } { 0.000ns 0.000ns 0.886ns 1.940ns 0.660ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.618ns } "" } } { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.381 ns" { pb db[0]~reg0 } "NODE_NAME" } } { "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.381 ns" { pb pb~combout db[0]~reg0 } { 0.000ns 0.000ns 3.781ns } { 0.000ns 0.854ns 0.746ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 15 10:18:48 2008 " "Info: Processing ended: Tue Apr 15 10:18:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}