prev_cmp_division_a.qmsg

正交方波信号的四细分功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 15 10:18:20 2008 " "Info: Processing started: Tue Apr 15 10:18:20 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off division_A -c division_A " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off division_A -c division_A" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 15 10:18:43 2008 " "Info: Processing ended: Tue Apr 15 10:18:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Info: Elapsed time: 00:00:23" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 15 10:18:45 2008 " "Info: Processing started: Tue Apr 15 10:18:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off division_A -c division_A --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off division_A -c division_A --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 2 -1 0 } } { "d:/program files/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "beginning~reg0 " "Info: Detected ripple clock \"beginning~reg0\" as buffer" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 12 0 0 } } { "d:/program files/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "beginning~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register db\[0\]~reg0 db\[7\]~reg0 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"db\[0\]~reg0\" and destination register \"db\[7\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.952 ns + Longest register register " "Info: + Longest register to register delay is 0.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns db\[0\]~reg0 1 REG LCFF_X5_Y10_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db\[0\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[0]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.309 ns) 0.520 ns Add0~130 2 COMB LCCOMB_X5_Y10_N16 2 " "Info: 2: + IC(0.211 ns) + CELL(0.309 ns) = 0.520 ns; Loc. = LCCOMB_X5_Y10_N16; Fanout = 2; COMB Node = 'Add0~130'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.520 ns" { db[0]~reg0 Add0~130 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.555 ns Add0~134 3 COMB LCCOMB_X5_Y10_N18 2 " "Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.555 ns; Loc. = LCCOMB_X5_Y10_N18; Fanout = 2; COMB Node = 'Add0~134'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~130 Add0~134 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.590 ns Add0~138 4 COMB LCCOMB_X5_Y10_N20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.590 ns; Loc. = LCCOMB_X5_Y10_N20; Fanout = 2; COMB Node = 'Add0~138'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~134 Add0~138 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.625 ns Add0~142 5 COMB LCCOMB_X5_Y10_N22 2 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.625 ns; Loc. = LCCOMB_X5_Y10_N22; Fanout = 2; COMB Node = 'Add0~142'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~138 Add0~142 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.660 ns Add0~146 6 COMB LCCOMB_X5_Y10_N24 2 " "Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 0.660 ns; Loc. = LCCOMB_X5_Y10_N24; Fanout = 2; COMB Node = 'Add0~146'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~142 Add0~146 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.695 ns Add0~150 7 COMB LCCOMB_X5_Y10_N26 2 " "Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 0.695 ns; Loc. = LCCOMB_X5_Y10_N26; Fanout = 2; COMB Node = 'Add0~150'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~146 Add0~150 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.730 ns Add0~154 8 COMB LCCOMB_X5_Y10_N28 1 " "Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 0.730 ns; Loc. = LCCOMB_X5_Y10_N28; Fanout = 1; COMB Node = 'Add0~154'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~150 Add0~154 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 0.855 ns Add0~157 9 COMB LCCOMB_X5_Y10_N30 1 " "Info: 9: + IC(0.000 ns) + CELL(0.125 ns) = 0.855 ns; Loc. = LCCOMB_X5_Y10_N30; Fanout = 1; COMB Node = 'Add0~157'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { Add0~154 Add0~157 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.097 ns) 0.952 ns db\[7\]~reg0 10 REG LCFF_X5_Y10_N31 2 " "Info: 10: + IC(0.000 ns) + CELL(0.097 ns) = 0.952 ns; Loc. = LCFF_X5_Y10_N31; Fanout = 2; REG Node = 'db\[7\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.097 ns" { Add0~157 db[7]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.741 ns ( 77.84 % ) " "Info: Total cell delay = 0.741 ns ( 77.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.211 ns ( 22.16 % ) " "Info: Total interconnect delay = 0.211 ns ( 22.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.952 ns" { db[0]~reg0 Add0~130 Add0~134 Add0~138 Add0~142 Add0~146 Add0~150 Add0~154 Add0~157 db[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "0.952 ns" { db[0]~reg0 Add0~130 Add0~134 Add0~138 Add0~142 Add0~146 Add0~150 Add0~154 Add0~157 db[7]~reg0 } { 0.000ns 0.211ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.309ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.125ns 0.097ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.670 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.712 ns) 2.452 ns beginning~reg0 2 REG LCFF_X6_Y10_N25 2 " "Info: 2: + IC(0.886 ns) + CELL(0.712 ns) = 2.452 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { clk beginning~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 12 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.940 ns) + CELL(0.000 ns) 4.392 ns beginning~reg0clkctrl 3 COMB CLKCTRL_G7 8 " "Info: 3: + IC(1.940 ns) + CELL(0.000 ns) = 4.392 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'beginning~reg0clkctrl'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.940 ns" { beginning~reg0 beginning~reg0clkctrl } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(0.618 ns) 5.670 ns db\[7\]~reg0 4 REG LCFF_X5_Y10_N31 2 " "Info: 4: + IC(0.660 ns) + CELL(0.618 ns) = 5.670 ns; Loc. = LCFF_X5_Y10_N31; Fanout = 2; REG Node = 'db\[7\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { beginning~reg0clkctrl db[7]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.184 ns ( 38.52 % ) " "Info: Total cell delay = 2.184 ns ( 38.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.486 ns ( 61.48 % ) " "Info: Total interconnect delay = 3.486 ns ( 61.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.670 ns" { clk beginning~reg0 beginning~reg0clkctrl db[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.670 ns" { clk clk~combout beginning~reg0 beginning~reg0clkctrl db[7]~reg0 } { 0.000ns 0.000ns 0.886ns 1.940ns 0.660ns } { 0.000ns 0.854ns 0.712ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.670 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.712 ns) 2.452 ns beginning~reg0 2 REG LCFF_X6_Y10_N25 2 " "Info: 2: + IC(0.886 ns) + CELL(0.712 ns) = 2.452 ns; Loc. = LCFF_X6_Y10_N25; Fanout = 2; REG Node = 'beginning~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { clk beginning~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 12 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.940 ns) + CELL(0.000 ns) 4.392 ns beginning~reg0clkctrl 3 COMB CLKCTRL_G7 8 " "Info: 3: + IC(1.940 ns) + CELL(0.000 ns) = 4.392 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'beginning~reg0clkctrl'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.940 ns" { beginning~reg0 beginning~reg0clkctrl } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(0.618 ns) 5.670 ns db\[0\]~reg0 4 REG LCFF_X5_Y10_N15 3 " "Info: 4: + IC(0.660 ns) + CELL(0.618 ns) = 5.670 ns; Loc. = LCFF_X5_Y10_N15; Fanout = 3; REG Node = 'db\[0\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { beginning~reg0clkctrl db[0]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.184 ns ( 38.52 % ) " "Info: Total cell del