prev_cmp_division_a.qmsg

正交方波信号的四细分功能

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.041 ns register register " "Info: Estimated most critical path is register to register delay of 1.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns db\[1\]~reg0 1 REG LAB_X5_Y10 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y10; Fanout = 3; REG Node = 'db\[1\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[1]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.236 ns) + CELL(0.350 ns) 0.586 ns Add0~134 2 COMB LAB_X5_Y10 2 " "Info: 2: + IC(0.236 ns) + CELL(0.350 ns) = 0.586 ns; Loc. = LAB_X5_Y10; Fanout = 2; COMB Node = 'Add0~134'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.586 ns" { db[1]~reg0 Add0~134 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.621 ns Add0~138 3 COMB LAB_X5_Y10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.621 ns; Loc. = LAB_X5_Y10; Fanout = 2; COMB Node = 'Add0~138'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~134 Add0~138 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.656 ns Add0~142 4 COMB LAB_X5_Y10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.656 ns; Loc. = LAB_X5_Y10; Fanout = 2; COMB Node = 'Add0~142'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~138 Add0~142 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.691 ns Add0~146 5 COMB LAB_X5_Y10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.691 ns; Loc. = LAB_X5_Y10; Fanout = 2; COMB Node = 'Add0~146'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~142 Add0~146 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.726 ns Add0~150 6 COMB LAB_X5_Y10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 0.726 ns; Loc. = LAB_X5_Y10; Fanout = 2; COMB Node = 'Add0~150'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~146 Add0~150 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.761 ns Add0~154 7 COMB LAB_X5_Y10 1 " "Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 0.761 ns; Loc. = LAB_X5_Y10; Fanout = 1; COMB Node = 'Add0~154'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~150 Add0~154 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 0.886 ns Add0~157 8 COMB LAB_X5_Y10 1 " "Info: 8: + IC(0.000 ns) + CELL(0.125 ns) = 0.886 ns; Loc. = LAB_X5_Y10; Fanout = 1; COMB Node = 'Add0~157'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { Add0~154 Add0~157 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.041 ns db\[7\]~reg0 9 REG LAB_X5_Y10 2 " "Info: 9: + IC(0.000 ns) + CELL(0.155 ns) = 1.041 ns; Loc. = LAB_X5_Y10; Fanout = 2; REG Node = 'db\[7\]~reg0'" {  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~157 db[7]~reg0 } "NODE_NAME" } } { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.805 ns ( 77.33 % ) " "Info: Total cell delay = 0.805 ns ( 77.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.236 ns ( 22.67 % ) " "Info: Total interconnect delay = 0.236 ns ( 22.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.041 ns" { db[1]~reg0 Add0~134 Add0~138 Add0~142 Add0~146 Add0~150 Add0~154 Add0~157 db[7]~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X12_Y13 " "Info: The peak interconnect region extends from location X0_Y0 to location X12_Y13" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "11 " "Warning: Found 11 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[0\] 0 " "Info: Pin \"db\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[1\] 0 " "Info: Pin \"db\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[2\] 0 " "Info: Pin \"db\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[3\] 0 " "Info: Pin \"db\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[4\] 0 " "Info: Pin \"db\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[5\] 0 " "Info: Pin \"db\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[6\] 0 " "Info: Pin \"db\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "db\[7\] 0 " "Info: Pin \"db\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pareg 0 " "Info: Pin \"pareg\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pbreg 0 " "Info: Pin \"pbreg\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "beginning 0 " "Info: Pin \"beginning\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Program Files/altera/division_A/division_A.fit.smsg " "Info: Generated suppressed messages file D:/Program Files/altera/division_A/division_A.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "213 " "Info: Allocated 213 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 15 10:18:16 2008 " "Info: Processing ended: Tue Apr 15 10:18:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Info: Elapsed time: 00:00:22" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}