prev_cmp_division_a.qmsg

正交方波信号的四细分功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 15 10:17:40 2008 " "Info: Processing started: Tue Apr 15 10:17:40 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off division_A -c division_A " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off division_A -c division_A" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "state division_A.v(7) " "Warning (10236): Verilog HDL Implicit Net warning at division_A.v(7): created implicit net for \"state\"" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 7 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "prestate division_A.v(8) " "Warning (10236): Verilog HDL Implicit Net warning at division_A.v(8): created implicit net for \"prestate\"" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 8 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "enable division_A.v(9) " "Warning (10236): Verilog HDL Implicit Net warning at division_A.v(9): created implicit net for \"enable\"" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 9 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "division_A.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file division_A.v" { { "Info" "ISGN_ENTITY_NAME" "1 division_A " "Info: Found entity 1: division_A" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "division_A " "Info: Elaborating entity \"division_A\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 division_A.v(7) " "Warning (10230): Verilog HDL assignment warning at division_A.v(7): truncated value with size 2 to match size of target (1)" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 7 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 division_A.v(8) " "Warning (10230): Verilog HDL assignment warning at division_A.v(8): truncated value with size 2 to match size of target (1)" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 8 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 division_A.v(9) " "Warning (10230): Verilog HDL assignment warning at division_A.v(9): truncated value with size 2 to match size of target (1)" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "division_A.v(22) " "Warning (10199): Verilog HDL Case Statement warning at division_A.v(22): case item expression never matches the case expression" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 22 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "division_A.v(23) " "Warning (10199): Verilog HDL Case Statement warning at division_A.v(23): case item expression never matches the case expression" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 23 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "division_A.v(24) " "Warning (10199): Verilog HDL Case Statement warning at division_A.v(24): case item expression never matches the case expression" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 24 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_CASE_CONDITION_REDUNDANT" "division_A.v(25) " "Warning (10199): Verilog HDL Case Statement warning at division_A.v(25): case item expression never matches the case expression" {  } { { "division_A.v" "" { Text "D:/Program Files/altera/division_A/division_A.v" 25 0 0 } }  } 0 10199 "Verilog HDL Case Statement warning at %1!s!: case item expression never matches the case expression" 0 0 "" 0}