📄 division_a.v.bak
字号:
module division_A(pa,pb,clk,db,pareg,pbreg,beginning);
input clk,pa,pb;
output [7:0] db;
output pareg,pbreg,beginning;
reg pareg,pbreg,beginning;
reg [7:0] db;
assign state={pa,pb};
assign prestate={pareg,pbreg};
assign enable={prestate,state};
//将PA,PB两状态合并作为状态的判断标志
always@(posedge clk) begin pareg<=pa; pbreg<=pb; end
always@(posedge clk) begin
if((pbreg!=pb)||(pareg!=pa))
beginning<=1;
else
beginning<=0;
end
//采用非阻塞赋值,将state当前状态的值赋给prestate;
always@(posedge beginning)
case(enable)
4'b0010:db<=db+4'b0001;
4'b1011:db<=db+4'b0001;
4'b1101:db<=db+4'b0001;
4'b0100:db<=db+4'b0001;
4'b0001:db<=db-4'b0001;
4'b0111:db<=db-4'b0001;
4'b1110:db<=db-4'b0001;
4'b1000:db<=db-4'b0001;
default
db<=db;
endcase
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -