gcd_wp.v

欧几里得算法求最大公约数电路的Verilog实现

module GCD(START,
           RST,
           CLK,
           OPA,
           OPB,
           DONE,
           RESULT);
           
	parameter	idle=3'b000;
    parameter	encode=3'b001;
    parameter	comp=3'b010;
    parameter	shift=3'b011;
    parameter	subtract=3'b111;
    parameter	load=3'b101;
    
    input	START,RST,CLK;
    input	[31:0] OPA;
    input	[31:0] OPB;
    
    output	DONE;
    output	[31:0] RESULT;
    
    wire START;
    wire RST;
    wire CLK;
    wire [31:0] OPA;
    wire [31:0] OPB;
    reg DONE;
    reg [31:0] RESULT;
    
    reg working;
    reg [31:0] ra;
    reg	[31:0] rb;
    reg [4:0] ha;
    reg [4:0] hb;
    reg [4:0] hc;
    reg [31:0] lar;
    reg [31:0] sma;
    reg [31:0] sub;
    reg [31:0] min;
    reg [31:0] min_2;

	always@(posedge CLK)
	begin
		if(!RST)
		begin
			ra<=32'b0;
			rb<=32'b0;
		end
		else if(!START)
		begin
			ra<=OPA;
			rb<=OPB;
		end
		else
		begin
			ra<=sub;
			rb<=sma;
		end
	end
    
    always@(posedge CLK)
    begin
    	if(!RST)
    	begin
    		DONE<=1'b0;
    		RESULT<=32'b0;
    	end
    	else if(sub==32'b0 && working==1'b1) 
    	begin 
    		DONE<=1'b1;      
        	RESULT<=sma; 
        end
        else
        begin
        	DONE<=1'b0;
        	RESULT<=32'b0;
        end
    end
    
    always@(posedge CLK)
    begin
    	if(!RST)
    	begin
    		working<=1'b0;
    	end
    	else if(!START)
    		working<=1'b1;
    	else if(DONE)
    		working<=1'b0;   	
    end
    
	always@(ra)
	begin
		casex(ra)                             //find the most significant bit of ra and encode as ha
           32'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11111;
           32'b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11110;
           32'b001xxxxxxxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11101;
           32'b0001xxxxxxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11100;
           32'b00001xxxxxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11011;
           32'b000001xxxxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11010;
           32'b0000001xxxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11001;
           32'b00000001xxxxxxxxxxxxxxxxxxxxxxxx: ha=5'b11000;
           32'b000000001xxxxxxxxxxxxxxxxxxxxxxx: ha=5'b10111;
           32'b0000000001xxxxxxxxxxxxxxxxxxxxxx: ha=5'b10110;
           32'b00000000001xxxxxxxxxxxxxxxxxxxxx: ha=5'b10101;
           32'b000000000001xxxxxxxxxxxxxxxxxxxx: ha=5'b10100;
           32'b0000000000001xxxxxxxxxxxxxxxxxxx: ha=5'b10011;
           32'b00000000000001xxxxxxxxxxxxxxxxxx: ha=5'b10010;
           32'b000000000000001xxxxxxxxxxxxxxxxx: ha=5'b10001;
           32'b0000000000000001xxxxxxxxxxxxxxxx: ha=5'b10000;
           32'b00000000000000001xxxxxxxxxxxxxxx: ha=5'b01111;
           32'b000000000000000001xxxxxxxxxxxxxx: ha=5'b01110;
           32'b0000000000000000001xxxxxxxxxxxxx: ha=5'b01101;
           32'b00000000000000000001xxxxxxxxxxxx: ha=5'b01100;
           32'b000000000000000000001xxxxxxxxxxx: ha=5'b01011;
           32'b0000000000000000000001xxxxxxxxxx: ha=5'b01010;
           32'b00000000000000000000001xxxxxxxxx: ha=5'b01001;
           32'b000000000000000000000001xxxxxxxx: ha=5'b01000;
           32'b0000000000000000000000001xxxxxxx: ha=5'b00111;
           32'b00000000000000000000000001xxxxxx: ha=5'b00110;
           32'b000000000000000000000000001xxxxx: ha=5'b00101;
           32'b0000000000000000000000000001xxxx: ha=5'b00100;
           32'b00000000000000000000000000001xxx: ha=5'b00011;
           32'b000000000000000000000000000001xx: ha=5'b00010;
           32'b0000000000000000000000000000001x: ha=5'b00001;
           32'b00000000000000000000000000000001: ha=5'b00000;
           default: ha=5'b00000;                     
        endcase
	end    
    
    always@(rb)
    begin
    	casex(rb)                      //find the most significant bit of rb and encode as hb
           32'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11111;
           32'b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11110;
           32'b001xxxxxxxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11101;
           32'b0001xxxxxxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11100;
           32'b00001xxxxxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11011;
           32'b000001xxxxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11010;
           32'b0000001xxxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11001;
           32'b00000001xxxxxxxxxxxxxxxxxxxxxxxx: hb=5'b11000;
           32'b000000001xxxxxxxxxxxxxxxxxxxxxxx: hb=5'b10111;
           32'b0000000001xxxxxxxxxxxxxxxxxxxxxx: hb=5'b10110;
           32'b00000000001xxxxxxxxxxxxxxxxxxxxx: hb=5'b10101;
           32'b000000000001xxxxxxxxxxxxxxxxxxxx: hb=5'b10100;
           32'b0000000000001xxxxxxxxxxxxxxxxxxx: hb=5'b10011;
           32'b00000000000001xxxxxxxxxxxxxxxxxx: hb=5'b10010;
           32'b000000000000001xxxxxxxxxxxxxxxxx: hb=5'b10001;
           32'b0000000000000001xxxxxxxxxxxxxxxx: hb=5'b10000;
           32'b00000000000000001xxxxxxxxxxxxxxx: hb=5'b01111;
           32'b000000000000000001xxxxxxxxxxxxxx: hb=5'b01110;
           32'b0000000000000000001xxxxxxxxxxxxx: hb=5'b01101;
           32'b00000000000000000001xxxxxxxxxxxx: hb=5'b01100;
           32'b000000000000000000001xxxxxxxxxxx: hb=5'b01011;
           32'b0000000000000000000001xxxxxxxxxx: hb=5'b01010;
           32'b00000000000000000000001xxxxxxxxx: hb=5'b01001;
           32'b000000000000000000000001xxxxxxxx: hb=5'b01000;
           32'b0000000000000000000000001xxxxxxx: hb=5'b00111;
           32'b00000000000000000000000001xxxxxx: hb=5'b00110;
           32'b000000000000000000000000001xxxxx: hb=5'b00101;
           32'b0000000000000000000000000001xxxx: hb=5'b00100;
           32'b00000000000000000000000000001xxx: hb=5'b00011;
           32'b000000000000000000000000000001xx: hb=5'b00010;
           32'b0000000000000000000000000000001x: hb=5'b00001;
           32'b00000000000000000000000000000001: hb=5'b00000;
           default:hb=5'b00000;
        endcase
    end
    
    always@(ra or rb or ha or hb)
    begin
    	if(ra>=rb)
    	begin
    		hc=ha-hb;
    		lar=ra;
    		sma=rb;
    	end
    	else
    	begin
    		hc=hb-ha;
    		lar=rb;
    		sma=ra;
    	end
    end
    
    always@(hc or sma)
    begin
    	case(hc)         
            5'd31: min=sma<<30;                  
            5'd30: min=sma<<29;
            5'd29: min=sma<<28;
            5'd28: min=sma<<27;
            5'd27: min=sma<<26;
            5'd26: min=sma<<25;
            5'd25: min=sma<<24;
            5'd24: min=sma<<23;
            5'd23: min=sma<<22;
            5'd22: min=sma<<21;
            5'd21: min=sma<<20;
            5'd20: min=sma<<19;
            5'd19: min=sma<<18;
            5'd18: min=sma<<17;
            5'd17: min=sma<<16;
            5'd16: min=sma<<15;
            5'd15: min=sma<<14;
            5'd14: min=sma<<13;
            5'd13: min=sma<<12;
            5'd12: min=sma<<11;
            5'd11: min=sma<<10;
            5'd10: min=sma<<9;
            5'd9: min=sma<<8;
            5'd8: min=sma<<7;
            5'd7: min=sma<<6;
            5'd6: min=sma<<5;
            5'd5: min=sma<<4;
            5'd4: min=sma<<3;
            5'd3: min=sma<<2;
            5'd2: min=sma<<1;
            5'd1: min=sma;
            5'd0: min=sma;
            default: min=sma;
        endcase
    end  
      
    always@(min)
    begin
    	min_2=min<<1;
    end    
    
    always@(lar or min or min_2)
    begin
    	if(lar>=min_2&&!min[31])
    		sub=lar-min_2;
    	else
    		sub=lar-min;
    end
    
         
  endmodule