gcd_tb.v

欧几里得算法求最大公约数电路的Verilog实现

`timescale 1ns/100ps

module gcd_tb;
    reg START,RST,CLK;   
    reg [31:0] OPA,OPB;
    wire DONE;
    wire [31:0] RESULT;
GCD g1(START,RST,CLK,OPA,OPB,DONE,RESULT);    

initial
CLK=0;
always
#10 CLK=~CLK;

initial
 begin
START=1;
RST=1;
OPA=32'b110001000101;
OPB=32'b100000011000;
#50 RST=0;
#100 RST=1;
#100 START=0;
#20 START=1;
#1000 START=0;
#20 START=1;
end 
endmodule