3.txt

频率计设计 由多个部分组成 主要为了学习VHDL的同学提供 加油 加油 加油 加油 加油 加油 加油

⑩進制計數器

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT10 IS
PORT(CLK,CLR,ENA:IN STD_LOGIC;
     CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
     CARRAY_OUT:OUT STD_LOGIC
    );
END CNT10;
ARCHITECTURE GYL OF CNT10 IS
BEGIN
PROCESS(CLK,CLR,ENA)
VARIABLE CQ1:STD_LOGIC_VECTOR(3 DOWNTO 0);
 BEGIN
 IF CLR='1' THEN CQ1:=(OTHERS=>'0');
  ELSIF CLK'EVENT AND CLK='1' THEN
  IF ENA='1' THEN
   IF CQ1<9 THEN CQ1:=CQ1+1;
   ELSE CQ1:=(OTHERS=>'0');
  END IF;
  END IF;
  END IF;
  IF CQ1=0 THEN CARRAY_OUT<='1';
  ELSE CARRAY_OUT <='0';
  END IF;
  CQ<=CQ1;
END PROCESS;
END GYL;
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七段數碼顯示器

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  LED  IS
    PORT (
          ADIN :  IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
          CK : IN  STD_LOGIC;
          SEG : OUT  STD_LOGIC_VECTOR (6 DOWNTO 0);
          SEL : OUT  STD_LOGIC_VECTOR (2 DOWNTO 0) 
          );
END  LED;
ARCHITECTURE  GYL OF LED IS
SIGNAL    NUM : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL    COUNT :STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
PROCESS (CK)
BEGIN
  IF CK'EVENT AND CK='1'  THEN
      IF  COUNT < 5  THEN
          COUNT<=COUNT + 1;
      ELSE COUNT <="000";
      END IF;
  END IF;    
END PROCESS;
SEL<=COUNT;
NUM<=ADIN(3 DOWNTO  0)  WHEN  COUNT=0  ELSE
     ADIN(7  DOWNTO  4)  WHEN  COUNT=1  ELSE
     ADIN(11 DOWNTO  8)  WHEN  COUNT=2  ELSE
     ADIN(15 DOWNTO 12)  WHEN  COUNT=3  ELSE
     ADIN(19 DOWNTO 16)  WHEN  COUNT=4  ELSE
     ADIN(23 DOWNTO 20);  
SEG<="0111111"  WHEN  NUM=0  ELSE
     "0000110"  WHEN  NUM=1  ELSE
     "1011011"  WHEN  NUM=2  ELSE
     "1001111"  WHEN  NUM=3  ELSE
     "1100110"  WHEN  NUM=4  ELSE
     "1101101"  WHEN  NUM=5  ELSE
     "1111101"  WHEN  NUM=6  ELSE
     "0000111"  WHEN  NUM=7  ELSE
     "1111111"  WHEN  NUM=8  ELSE
     "1101111"  WHEN  NUM=9  ELSE
     "1110111"  WHEN  NUM=10 ELSE
     "1111100"  WHEN  NUM=11 ELSE
     "0111001"  WHEN  NUM=12 ELSE
     "1011110"  WHEN  NUM=13 ELSE
     "1111001"  WHEN  NUM=14 ELSE
     "1110001"  WHEN  NUM=15 ELSE
     "0000000";
END GYL;       
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24位寄存器模塊

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG IS
  PORT (LOAD: IN STD_LOGIC;
        DIN: IN STD_LOGIC_VECTOR(23 DOWNTO 0) ;
        DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
        );
END ENTITY REG;
ARCHITECTURE GYL OF REG IS
SIGNAL RE:STD_LOGIC_VECTOR(23 DOWNTO 0);
 BEGIN
PROCESS(LOAD)
 BEGIN
 IF LOAD'EVENT AND LOAD='1'
  THEN RE<=DIN;
 END IF;
 DOUT<=RE;
 END PROCESS;
END ARCHITECTURE GYL;
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===============================================================
測頻控制信號發生器TESTCTL

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TESTCTL IS
PORT(CLK:IN STD_LOGIC;
     LOAD,CLR_CNT:OUT STD_LOGIC;
     TSTEN:BUFFER STD_LOGIC
     );
END TESTCTL;
ARCHITECTURE GYL OF TESTCTL IS
SIGNAL TC:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL Q:STD_LOGIC;
 BEGIN
 TC<=CLK&Q;
 PROCESS(CLK)
   BEGIN
   IF CLK'EVENT AND CLK='1' THEN TSTEN<=NOT TSTEN;
  
   END IF;
   Q<=TSTEN;
   LOAD<=NOT Q;
   CASE TC IS
    WHEN "00"=>CLR_CNT<='1';
    WHEN "01"=>CLR_CNT<='0';
    WHEN "10"=>CLR_CNT<='0';
    WHEN "11"=>CLR_CNT<='0';
    WHEN OTHERS=>NULL;
   END CASE;
   END PROCESS;
END GYL; 
     
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===============================================================
完整頻率計

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PLJ IS
PORT(FSIN,CLK,SCAN:IN STD_LOGIC;
     SEG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
     SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
     );
END PLJ;
ARCHITECTURE  GYL OF PLJ IS
COMPONENT TESTCTL 
PORT(CLK:IN STD_LOGIC;
     LOAD,CLR_CNT:OUT STD_LOGIC;
     TSTEN:BUFFER STD_LOGIC
     );
END COMPONENT;

COMPONENT CNT10 
PORT(CLK,CLR,ENA:IN STD_LOGIC;
     CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
     CARRAY_OUT:OUT STD_LOGIC
    );
END COMPONENT;

COMPONENT REG 
  PORT (LOAD: IN STD_LOGIC;
        DIN: IN STD_LOGIC_VECTOR(23 DOWNTO 0) ;
        DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
        );
END COMPONENT;

COMPONENT LED  
    PORT (
          ADIN :  IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
          CK : IN  STD_LOGIC;
          SEG : OUT  STD_LOGIC_VECTOR (6 DOWNTO 0);
          SEL : OUT  STD_LOGIC_VECTOR (2 DOWNTO 0) 
          );
END  COMPONENT;
SIGNAL A,B,C,F1,F2,F3,F4,F5:STD_LOGIC;
SIGNAL D:STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL DT:STD_LOGIC_VECTOR(23 DOWNTO 0); 
 BEGIN
 U1:TESTCTL PORT MAP(CLK=>CLK,TSTEN=>A,CLR_CNT=>B,LOAD=>C);
 U2:CNT10 PORT MAP(CLK=>FSIN,CLR=>B,ENA=>A,CARRAY_OUT=>F1,CQ(3 DOWNTO 0)=>D(3 DOWNTO 0));
 U3:CNT10 PORT MAP(CLK=>F1,CLR=>B,ENA=>A,CARRAY_OUT=>F2,CQ(3 DOWNTO 0)=>D(7 DOWNTO 4));
 U4:CNT10 PORT MAP(CLK=>F2,CLR=>B,ENA=>A,CARRAY_OUT=>F3,CQ(3 DOWNTO 0)=>D(11 DOWNTO 8));
 U5:CNT10 PORT MAP(CLK=>F3,CLR=>B,ENA=>A,CARRAY_OUT=>F4,CQ(3 DOWNTO 0)=>D(15 DOWNTO 12));
 U6:CNT10 PORT MAP(CLK=>F4,CLR=>B,ENA=>A,CARRAY_OUT=>F5,CQ(3 DOWNTO 0)=>D(19 DOWNTO 16));
 U7:CNT10 PORT MAP(CLK=>F5,CLR=>B,ENA=>A,CQ(3 DOWNTO 0)=>D(23 DOWNTO 20));
 U8:REG PORT MAP(LOAD=>C,DIN(3 DOWNTO 0)=>D(3 DOWNTO 0),DIN(7 DOWNTO 4)=>D(7 DOWNTO 4),DIN(11 DOWNTO 8)=>D(11 DOWNTO 8),DIN(15 DOWNTO 12)=>D(15 DOWNTO 12),DIN(19 DOWNTO 16)=>D(19 DOWNTO 16),DIN(23 DOWNTO 20)=>D(23 DOWNTO 20),DOUT(23 DOWNTO 0)=>DT(23 DOWNTO 0));
 U9:LED PORT MAP(CK=>SCAN,ADIN(23 DOWNTO 0)=>DT(23 DOWNTO 0),SEG(6 DOWNTO 0)=>SEG(6 DOWNTO 0),SEL(2 DOWNTO 0)=>SEL(2 DOWNTO 0));
END GYL;