_primary.vhd

来自「用verilog鉴定10010序列」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity lpm_outpad is
    generic(
        lpm_width       : integer := 1;
        lpm_type        : string  := "lpm_outpad";
        lpm_hint        : string  := "UNUSED"
    );
    port(
        data            : in     vl_logic_vector;
        pad             : out    vl_logic_vector
    );
end lpm_outpad;