_primary.vhd

来自「用verilog鉴定10010序列」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity altstratixii_oct is
    generic(
        lpm_type        : string  := "altstratixii_oct"
    );
    port(
        terminationenable: in     vl_logic;
        terminationclock: in     vl_logic;
        rdn             : in     vl_logic;
        rup             : in     vl_logic
    );
end altstratixii_oct;