_primary.vhd

来自「用verilog鉴定10010序列」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity srffe is
    port(
        s               : in     vl_logic;
        r               : in     vl_logic;
        clk             : in     vl_logic;
        ena             : in     vl_logic;
        clrn            : in     vl_logic;
        prn             : in     vl_logic;
        q               : out    vl_logic
    );
end srffe;