shiyan4.vhd

来自「这是一个两个状态机的文件 都是很输入有关的 是我很我的同学的 希望对大家还是有点」· VHDL 代码 · 共 89 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity shiyan4 is
	port(clk,reset: in std_logic;
		 control: in std_logic_vector(1 downto 0);
		 output : out bit_vector(7 downto 0));
		end entity;
		
architecture flash of shiyan4 is
	type state is (st0,st1,st2,st3);
	signal pr_state,nx_state : state;
	signal i:integer;
	begin
	
	process(clk,reset)
	begin	
		if(reset='1')then
			pr_state<=st0;
			elsif(clk'event and clk='1')then
				pr_state<=nx_state;
		end if;
		end process;
		
		process(clk,i)
		begin
		if(clk'event and clk='1')then
			if(i=7)then
			i<=0;
			else
			i<=i+1;
			end if;
			end if;
			end process;
		
		process(control,pr_state,i) is
		begin
			case pr_state is
				when st0=>
				 	output<="10101010" rol i;
				if(control="01")then
					nx_state<=st1;
				elsif(control="10")then
					nx_state<=st2;
				elsif(control="11")then
				    nx_state<=st3;
				else
					nx_state<=st0;
					end if;
					
				when st1=>
					output<="00000001" rol i;
				if(control="00")then
					nx_state<=st0;
				elsif(control="10")then
					nx_state<=st2;
				elsif(control="11")then
					nx_state<=st3;
				else
					nx_state<=st1;
					end if;
				
				when st2=>
					output<="11111110" rol i;
				if(control="00")then
					nx_state<=st0;
				elsif(control="01")then
					nx_state<=st1;
				elsif(control="11")then
					nx_state<=st3;
					else
						nx_state<=st2;
					end if;
					
					when others=>
					output<="00001111" rol i;
				if(control="00")then
					nx_state<=st0;
				elsif(control="01")then
					nx_state<=st1;
				elsif(control="01")then
				    nx_state<=st2;
				else
					nx_state<=st3;
				end if;
					end case;
					end process;
					end architecture;