test4.vhd

这是一个两个状态机的文件 都是很输入有关的 是我很我的同学的 希望对大家还是有点帮助的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_1164.STD_ULOGIC;
ENTITY TEST4 IS
PORT(
RESET,CON,CLK:IN STD_LOGIC;
OUT1:OUT BIT_VECTOR(7 DOWNTO 0)
);
END ENTITY TEST4;
ARCHITECTURE MAIN OF TEST4 IS
SIGNAL TEMP:BIT_VECTOR(7 DOWNTO 0);
SIGNAL TEMP1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL TEMP2:STD_LOGIC_VECTOR(1 DOWNTO 0);
TYPE STATES IS(S0,S1,S2,S3);
SIGNAL CURRENT_STATE:STATES;
SIGNAL NEXT_STATE:STATES;
BEGIN
P1:PROCESS(CURRENT_STATE)
BEGIN
CASE CURRENT_STATE IS
WHEN S0=>
NEXT_STATE<=S1;
WHEN S1=>
NEXT_STATE<=S2;
WHEN S2=>
NEXT_STATE<=S3;
WHEN S3=>
NEXT_STATE<=S0;
WHEN OTHERS=>
NEXT_STATE<=S0;
END CASE;
END PROCESS P1;
------------------------------------------------------------------------
P2:PROCESS(CON)
BEGIN
IF RESET='1' THEN
CURRENT_STATE<=S0;
ELSIF(CON'EVENT AND CON='1') THEN
CURRENT_STATE<=NEXT_STATE;
END IF;
END PROCESS P2;
------------------------------------------------------------------------
P3:PROCESS(CLK)
variable DATA:integer range 0 to 8;
variable DATA1:integer range 0 to 8;
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
DATA1:=DATA1+1;
IF(DATA1=8) THEN
DATA:=DATA+1;
DATA1:=0;
IF(DATA=8) THEN
DATA:=0;
end if;
CASE CURRENT_STATE IS
WHEN S0=> 
OUT1<="00000001" ROL DATA;
WHEN S1=> 
OUT1<="00000011" ROL DATA;
WHEN S2=> 
OUT1<="00001111" ROL DATA;
WHEN S3=> 
OUT1<="10101010" ROL DATA;
WHEN OTHERS=>
OUT1<="00000000";
END CASE;
END IF;
END IF;
END PROCESS P3;
END ARCHITECTURE MAIN;