📄 test7.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TEST7 IS
PORT(IN1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ON1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK,CON:IN STD_LOGIC;
OUT2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
OUT1:BUFFER STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END ENTITY TEST7;
ARCHITECTURE MAIN OF TEST7 IS
signal A:STD_LOGIC_VECTOR( 4 DOWNTO 0);
SIGNAL B,C,D:STD_LOGIC;
SIGNAL E:STD_LOGIC_VECTOR(1 DOWNTO 0);
type SEG7 is array (0 to 16) of std_logic_vector(7 downto 0);
constant seven_seg: SEG7 := (
"00111111",
"00000110",
"01011011",
"01001111",
"01100110",
"01101101",
"01111101",
"00000111",
"01111111",
"01100111",
"01110111",
"01111100",
"00111001",
"01011110",
"01111001",
"01110001",
"ZZZZZZZZ"
);
BEGIN
----------------------------------------------------------
P:PROCESS(CLK)
VARIABLE Z:INTEGER RANGE 0 TO 6;
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
Z:=Z+1;
IF(CON='1') THEN
A<="10000";
B<='1';
ELSE
B<='0';
A<=A;
END IF;
IF(Z=0) THEN
ON1<="0001";
IF(IN1="0001") THEN
A<="01100";
B<='1';
ELSIF(IN1="0010") THEN
A<="01101";
B<='1';
ELSIF(IN1="0100") THEN
A<="01110";
B<='1';
ELSIF(IN1="1000") THEN
A<="01111";
B<='1';
ELSE
A<=A;
B<='0';
END IF;
------------------------
ELSIF(Z=2) THEN
ON1<="0010";
IF(IN1="0001") THEN
A<="00000";
B<='1';
ELSIF(IN1="0010") THEN
A<="00001";
B<='1';
ELSIF(IN1="0100") THEN
A<="00010";
B<='1';
ELSIF(IN1="1000") THEN
A<="00011";
B<='1';
ELSE
A<=A;
B<='0';
END IF;
ELSIF(Z=4) THEN
ON1<="0100";
IF(IN1="0001") THEN
A<="00100";
B<='1';
ELSIF(IN1="0010") THEN
A<="00101";
B<='1';
ELSIF(IN1="0100") THEN
A<="00110";
B<='1';
ELSIF(IN1="1000") THEN
A<="00111";
B<='1';
ELSE
A<=A;
B<='0';
END IF;
------------------------------
ELSIF(Z=6) THEN
ON1<="1000";
IF(IN1="0001") THEN
A<="01000";
B<='1';
ELSIF(IN1="0010") THEN
A<="01001";
B<='1';
ELSIF(IN1="0100") THEN
A<="01010";
B<='1';
ELSIF(IN1="1000") THEN
A<="01011";
B<='1';
ELSE
A<=A;
B<='0';
END IF;
--------------------------------
end if;
end if;
END PROCESS P;
--------------------------------------------------------
P1:PROCESS(B)
BEGIN
IF(B='1') THEN
OUT1<=A;
ELSE
OUT2<=seven_seg(CONV_INTEGER(OUT1));
END IF;
END PROCESS P1;
------------------------------------------------------------------
END ARCHITECTURE;
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