cpld_qq2812.v.bak

QQ2812开发板的CPLD源代码

//Read Add

//Write Add
`define W_BUZZER			6'h00


module cpld_QQ2812(DSP_Add,DSP_Data,WR,RD,CS1,BUZZER);

input [5:0] DSP_Add;
input WR,RD,CS1;

output BUZZER;

inout [7:0]DSP_Data;

reg [7:0] DSP_Data_reg;
reg BUZZER_reg;

always @ (  negedge CS1)
begin
if(WR==1'b0)
    begin
		case (DSP_Add)
        	`W_BUZZER:BUZZER_reg=DSP_Data[0];
		endcase
	 end
else if(RD==1'b0)
  begin
  end
end

assign  BUZZER=BUZZER_reg;
assign  DSP_Data = (CS1 == 1'b0 && RD == 1'b0) ? DSP_Data_reg:8'hz; 

endmodule