prev_cmp_sram4m.tan.qmsg

Altera cyclone ep1c6对sram idt71系列的读写时序控制

{ "Info" "ITDB_TSU_RESULT" "bt860_data\[7\]\$latch bt835_field bt835_vreset 8.121 ns register " "Info: tsu for register \"bt860_data\[7\]\$latch\" (data pin = \"bt835_field\", clock pin = \"bt835_vreset\") is 8.121 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.014 ns + Longest pin register " "Info: + Longest pin to register delay is 15.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns bt835_field 1 CLK PIN_20 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_20; Fanout = 5; CLK Node = 'bt835_field'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { bt835_field } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.018 ns) + CELL(0.292 ns) 7.779 ns dio_2\[0\]~44 2 COMB LC_X8_Y10_N0 8 " "Info: 2: + IC(6.018 ns) + CELL(0.292 ns) = 7.779 ns; Loc. = LC_X8_Y10_N0; Fanout = 8; COMB Node = 'dio_2\[0\]~44'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.310 ns" { bt835_field dio_2[0]~44 } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.153 ns) + CELL(0.590 ns) 12.522 ns bt860_data\[7\]~674 3 COMB LC_X34_Y16_N6 1 " "Info: 3: + IC(4.153 ns) + CELL(0.590 ns) = 12.522 ns; Loc. = LC_X34_Y16_N6; Fanout = 1; COMB Node = 'bt860_data\[7\]~674'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.743 ns" { dio_2[0]~44 bt860_data[7]~674 } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.902 ns) + CELL(0.590 ns) 15.014 ns bt860_data\[7\]\$latch 4 REG LC_X34_Y4_N2 1 " "Info: 4: + IC(1.902 ns) + CELL(0.590 ns) = 15.014 ns; Loc. = LC_X34_Y4_N2; Fanout = 1; REG Node = 'bt860_data\[7\]\$latch'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.492 ns" { bt860_data[7]~674 bt860_data[7]$latch } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 37 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.941 ns ( 19.59 % ) " "Info: Total cell delay = 2.941 ns ( 19.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.073 ns ( 80.41 % ) " "Info: Total interconnect delay = 12.073 ns ( 80.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "15.014 ns" { bt835_field dio_2[0]~44 bt860_data[7]~674 bt860_data[7]$latch } "NODE_NAME" } } { "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "15.014 ns" { bt835_field {} bt835_field~out0 {} dio_2[0]~44 {} bt860_data[7]~674 {} bt860_data[7]$latch {} } { 0.000ns 0.000ns 6.018ns 4.153ns 1.902ns } { 0.000ns 1.469ns 0.292ns 0.590ns 0.590ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.842 ns + " "Info: + Micro setup delay of destination is 0.842 ns" {  } { { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 37 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bt835_vreset destination 7.735 ns - Shortest register " "Info: - Shortest clock path from clock \"bt835_vreset\" to destination register is 7.735 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns bt835_vreset 1 CLK PIN_23 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 23; CLK Node = 'bt835_vreset'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { bt835_vreset } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.012 ns) + CELL(0.114 ns) 3.595 ns bt860_data\[6\]~667 2 COMB LC_X8_Y10_N7 8 " "Info: 2: + IC(2.012 ns) + CELL(0.114 ns) = 3.595 ns; Loc. = LC_X8_Y10_N7; Fanout = 8; COMB Node = 'bt860_data\[6\]~667'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.126 ns" { bt835_vreset bt860_data[6]~667 } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.026 ns) + CELL(0.114 ns) 7.735 ns bt860_data\[7\]\$latch 3 REG LC_X34_Y4_N2 1 " "Info: 3: + IC(4.026 ns) + CELL(0.114 ns) = 7.735 ns; Loc. = LC_X34_Y4_N2; Fanout = 1; REG Node = 'bt860_data\[7\]\$latch'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.140 ns" { bt860_data[6]~667 bt860_data[7]$latch } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 37 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.697 ns ( 21.94 % ) " "Info: Total cell delay = 1.697 ns ( 21.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.038 ns ( 78.06 % ) " "Info: Total interconnect delay = 6.038 ns ( 78.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.735 ns" { bt835_vreset bt860_data[6]~667 bt860_data[7]$latch } "NODE_NAME" } } { "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "7.735 ns" { bt835_vreset {} bt835_vreset~out0 {} bt860_data[6]~667 {} bt860_data[7]$latch {} } { 0.000ns 0.000ns 2.012ns 4.026ns } { 0.000ns 1.469ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "15.014 ns" { bt835_field dio_2[0]~44 bt860_data[7]~674 bt860_data[7]$latch } "NODE_NAME" } } { "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "15.014 ns" { bt835_field {} bt835_field~out0 {} dio_2[0]~44 {} bt860_data[7]~674 {} bt860_data[7]$latch {} } { 0.000ns 0.000ns 6.018ns 4.153ns 1.902ns } { 0.000ns 1.469ns 0.292ns 0.590ns 0.590ns } "" } } { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.735 ns" { bt835_vreset bt860_data[6]~667 bt860_data[7]$latch } "NODE_NAME" } } { "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "7.735 ns" { bt835_vreset {} bt835_vreset~out0 {} bt860_data[6]~667 {} bt860_data[7]$latch {} } { 0.000ns 0.000ns 2.012ns 4.026ns } { 0.000ns 1.469ns 0.114ns 0.114ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "bt835_vreset adr_1\[0\] res1 59.725 ns register " "Info: tco from clock \"bt835_vreset\" to destination pin \"adr_1\[0\]\" through register \"res1\" is 59.725 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bt835_vreset source 8.061 ns + Longest register " "Info: + Longest clock path from clock \"bt835_vreset\" to source register is 8.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns bt835_vreset 1 CLK PIN_23 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 23; CLK Node = 'bt835_vreset'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { bt835_vreset } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.998 ns) + CELL(0.442 ns) 3.909 ns res1~1 2 COMB LC_X8_Y10_N6 2 " "Info: 2: + IC(1.998 ns) + CELL(0.442 ns) = 3.909 ns; Loc. = LC_X8_Y10_N6; Fanout = 2; COMB Node = 'res1~1'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.440 ns" { bt835_vreset res1~1 } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.038 ns) + CELL(0.114 ns) 8.061 ns res1 3 REG LC_X30_Y8_N8 58 " "Info: 3: + IC(4.038 ns) + CELL(0.114 ns) = 8.061 ns; Loc. = LC_X30_Y8_N8; Fanout = 58; REG Node = 'res1'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.152 ns" { res1~1 res1 } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.025 ns ( 25.12 % ) " "Info: Total cell delay = 2.025 ns ( 25.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.036 ns ( 74.88 % ) " "Info: Total interconnect delay = 6.036 ns ( 74.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "8.061 ns" { bt835_vreset res1~1 res1 } "NODE_NAME" } } { "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/quartus7.2/quartus/bin/Technology_Viewer.qrui" "8.061 ns" { bt835_vreset {} bt835_vreset~out0 {} res1~1 {} res1 {} } { 0.000ns 0.000ns 1.998ns 4.038ns } { 0.000ns 1.469ns 0.442ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "51.664 ns + Longest register pin " "Info: + Longest register to pin delay is 51.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns res1 1 REG LC_X30_Y8_N8 58 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y8_N8; Fanout = 58; REG Node = 'res1'" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { res1 } "NODE_NAME" } } { "sram4m.vhd" "" { Text "D:/sram4m/sram4m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(47.732 ns) 47.732 ns addr1\[0\]~1333 2 COMB LOOP LC_X30_Y8_N6 2 " "Info: 2: + IC(0.000 ns) + CELL(47.732 ns) = 47.732 ns; Loc. = LC_X30_Y8_N6; Fanout = 2; COMB LOOP Node = 'addr1\[0\]~1333'" { { "Info" "ITDB_PART_OF_SCC" "Add0~47 LC_X29_Y9_N1 " "Info: Loc. = LC_X29_Y9_N1; Node \"Add0~47\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~47 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~50 LC_X29_Y9_N2 " "Info: Loc. = LC_X29_Y9_N2; Node \"Add0~50\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~50 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~56COUT1 LC_X29_Y9_N5 " "Info: Loc. = LC_X29_Y9_N5; Node \"Add0~56COUT1\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~56COUT1 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~63 LC_X29_Y9_N9 " "Info: Loc. = LC_X29_Y9_N9; Node \"Add0~63\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~63 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "process1~81 LC_X30_Y8_N1 " "Info: Loc. = LC_X30_Y8_N1; Node \"process1~81\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { process1~81 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~52COUT1 LC_X29_Y9_N3 " "Info: Loc. = LC_X29_Y9_N3; Node \"Add0~52COUT1\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~52COUT1 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "addr1\[7\]~1337 LC_X30_Y9_N5 " "Info: Loc. = LC_X30_Y9_N5; Node \"addr1\[7\]~1337\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr1[7]~1337 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~49 LC_X29_Y9_N2 " "Info: Loc. = LC_X29_Y9_N2; Node \"Add0~49\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~49 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~56 LC_X29_Y9_N5 " "Info: Loc. = LC_X29_Y9_N5; Node \"Add0~56\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~56 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "addr1\[8\]~1326 LC_X29_Y8_N1 " "Info: Loc. = LC_X29_Y8_N1; Node \"addr1\[8\]~1326\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr1[8]~1326 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~52 LC_X29_Y9_N3 " "Info: Loc. = LC_X29_Y9_N3; Node \"Add0~52\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~52 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~58COUT1 LC_X29_Y9_N6 " "Info: Loc. = LC_X29_Y9_N6; Node \"Add0~58COUT1\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~58COUT1 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~55 LC_X29_Y9_N5 " "Info: Loc. = LC_X29_Y9_N5; Node \"Add0~55\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~55 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "addr1\[8\]~1338 LC_X30_Y9_N2 " "Info: Loc. = LC_X30_Y9_N2; Node \"addr1\[8\]~1338\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr1[8]~1338 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~66COUT1 LC_X29_Y9_N0 " "Info: Loc. = LC_X29_Y9_N0; Node \"Add0~66COUT1\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { Add0~66COUT1 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "Add0~51 LC_X29_Y9_N3 " "Info: Loc. = LC_X29_Y9_N3; Node \"Add0~51\"" {  } { { "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus7.2/quartus/bin/TimingClosureFloorplan